Kerry Sheh | 134d8a9 | 2012-02-07 20:33:21 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
Paul Menzel | a46a712 | 2013-02-23 18:37:27 +0100 | [diff] [blame] | 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Kerry Sheh | 134d8a9 | 2012-02-07 20:33:21 +0800 | [diff] [blame] | 18 | */ |
| 19 | |
| 20 | #ifndef _W83795_H_ |
| 21 | #define _W83795_H_ |
| 22 | |
| 23 | #define W83795_DEV 0x2F /* Host I2c Addr (strap to addr1 addr0 1 1, 0x5E) */ |
| 24 | |
| 25 | #define W83795_REG_I2C_ADDR 0xFC |
| 26 | #define W83795_REG_BANKSEL 0x00 |
| 27 | #define W83795_REG_CONFIG 0x01 |
| 28 | #define W83795_REG_CONFIG_START 0x01 |
| 29 | #define W83795_REG_CONFIG_CONFIG48 0x04 |
| 30 | #define W83795_REG_CONFIG_INIT 0x80 |
| 31 | |
| 32 | #define W83795_REG_TEMP_CTRL1 0x04 /* Temperature Monitoring Control Register */ |
| 33 | #define W83795_REG_TEMP_CTRL2 0x05 /* Temperature Monitoring Control Register */ |
| 34 | #define W83795_REG_FANIN_CTRL1 0x06 |
| 35 | #define W83795_REG_FANIN_CTRL2 0x07 |
| 36 | #define W83795_REG_TEMP_CTRL1_EN_DTS 0x20 /* Enable DTS (Digital Temperature Sensor) interface from INTEL PECI or AMD SB-TSI. */ |
| 37 | #define DTS_SRC_INTEL_PECI (0 << 0) |
| 38 | #define DTS_SRC_AMD_SBTSI (1 << 0) |
| 39 | |
| 40 | #define W83795_REG_TSS(n) (0x209 + (n)) /* Temperature Source Selection Register */ |
| 41 | #define W83795_REG_TTTI(n) (0x260 + (n)) /* tarrget temperature W83795G/ADG will try to tune the fan output to keep */ |
| 42 | #define W83795_REG_CTFS(n) (0x268 + (n)) /* Critical Temperature to Full Speed all fan */ |
| 43 | #define W83795_REG_HT(n) (0x270 + (n)) /* Hystersis of Temperature */ |
| 44 | #define W83795_REG_DTSC 0x301 /* Digital Temperature Sensor Configuration */ |
| 45 | |
| 46 | #define W83795_REG_DTSE 0x302 /* Digital Temperature Sensor Enable */ |
| 47 | #define W83795_REG_DTS(n) (0x26 + (n)) |
| 48 | #define W83795_REG_VRLSB 0x3C |
| 49 | |
| 50 | #define W83795_TEMP_REG_TR1 0x21 |
| 51 | #define W83795_TEMP_REG_TR2 0x22 |
| 52 | #define W83795_TEMP_REG_TR3 0x23 |
| 53 | #define W83795_TEMP_REG_TR4 0x24 |
| 54 | #define W83795_TEMP_REG_TR5 0x1F |
| 55 | #define W83795_TEMP_REG_TR6 0x20 |
| 56 | |
| 57 | #define W83795_REG_FCMS1 0x201 |
| 58 | #define W83795_REG_FCMS2 0x208 |
| 59 | #define W83795_REG_TFMR(n) (0x202 + (n)) /*temperature to fam mappig*/ |
| 60 | #define W83795_REG_DFSP 0x20C |
| 61 | |
| 62 | #define W83795_REG_FTSH(n) (0x240 + (n) * 2) |
| 63 | #define W83795_REG_FTSL(n) (0x241 + (n) * 2) |
| 64 | #define W83795_REG_TFTS 0x250 |
| 65 | |
| 66 | typedef enum w83795_fan_mode { |
| 67 | SPEED_CRUISE_MODE, ///< Fan Speed Cruise mode keeps the fan speed in a specified range |
| 68 | THERMAL_CRUISE_MODE, ///< Thermal Cruise mode is an algorithm to control the fan speed to keep the temperature source around the TTTI |
| 69 | SMART_FAN_MODE, ///< Smart Fan mode offers 6 slopes to control the fan speed |
| 70 | MANUAL_MODE, ///< control manually |
| 71 | } w83795_fan_mode_t; |
| 72 | |
| 73 | #endif |