Jonathan Zhang | 3ed903f | 2023-01-25 11:37:27 -0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <arch/ioapic.h> |
| 4 | #include <console/console.h> |
| 5 | #include <console/debug.h> |
| 6 | #include <cpu/x86/lapic.h> |
| 7 | #include <device/pci.h> |
| 8 | #include <device/pci_ids.h> |
| 9 | #include <device/pciexp.h> |
| 10 | #include <intelblocks/gpio.h> |
| 11 | #include <intelblocks/lpc_lib.h> |
| 12 | #include <intelblocks/p2sb.h> |
| 13 | #include <intelblocks/pcr.h> |
| 14 | #include <intelblocks/tco.h> |
| 15 | #include <soc/acpi.h> |
| 16 | #include <soc/chip_common.h> |
| 17 | #include <soc/crashlog.h> |
| 18 | #include <soc/numa.h> |
| 19 | #include <soc/p2sb.h> |
| 20 | #include <soc/pch.h> |
| 21 | #include <soc/soc_pch.h> |
| 22 | #include <soc/pci_devs.h> |
| 23 | #include <soc/ramstage.h> |
| 24 | #include <soc/soc_util.h> |
| 25 | #include <soc/util.h> |
| 26 | #include <soc/xhci.h> |
| 27 | |
| 28 | __weak void mainboard_silicon_init_params(FSPS_UPD *params) |
| 29 | { |
| 30 | |
| 31 | } |
| 32 | |
| 33 | /* UPD parameters to be initialized before SiliconInit */ |
| 34 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) |
| 35 | { |
| 36 | mainboard_silicon_init_params(silupd); |
| 37 | } |
| 38 | |
| 39 | #if CONFIG(HAVE_ACPI_TABLES) |
| 40 | const char *soc_acpi_name(const struct device *dev); |
| 41 | const char *soc_acpi_name(const struct device *dev) |
| 42 | { |
| 43 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 44 | return "PC00"; |
| 45 | return NULL; |
| 46 | } |
| 47 | #endif |
| 48 | |
| 49 | static struct device_operations pci_domain_ops = { |
| 50 | .read_resources = &pci_domain_read_resources, |
| 51 | .set_resources = &xeonsp_pci_domain_set_resources, |
| 52 | .scan_bus = &xeonsp_pci_domain_scan_bus, |
| 53 | #if CONFIG(HAVE_ACPI_TABLES) |
| 54 | .write_acpi_tables = &northbridge_write_acpi_tables, |
| 55 | .acpi_name = soc_acpi_name |
| 56 | #endif |
| 57 | }; |
| 58 | |
| 59 | static struct device_operations cpu_bus_ops = { |
| 60 | .read_resources = noop_read_resources, |
| 61 | .set_resources = noop_set_resources, |
| 62 | .init = mp_cpu_bus_init, |
| 63 | .acpi_fill_ssdt = generate_cpu_entries, |
| 64 | }; |
| 65 | |
| 66 | struct pci_operations soc_pci_ops = { |
| 67 | .set_subsystem = pci_dev_set_subsystem, |
| 68 | }; |
| 69 | |
| 70 | static void chip_enable_dev(struct device *dev) |
| 71 | { |
| 72 | /* Set the operations if it is a special bus type */ |
| 73 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 74 | dev->ops = &pci_domain_ops; |
| 75 | attach_iio_stacks(dev); |
| 76 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 77 | dev->ops = &cpu_bus_ops; |
| 78 | } else if (dev->path.type == DEVICE_PATH_GPIO) { |
| 79 | block_gpio_enable(dev); |
| 80 | } |
| 81 | } |
| 82 | |
| 83 | static void pcu_pci_or_config32(u8 bus, u8 func, u32 reg, u32 orval) |
| 84 | { |
| 85 | u32 data; |
| 86 | const uint32_t pcie_offset = PCI_DEV(bus, PCU_DEV, func); |
| 87 | |
| 88 | data = pci_s_read_config32(pcie_offset, reg); |
| 89 | data |= orval; |
| 90 | pci_s_write_config32(pcie_offset, reg, data); |
| 91 | } |
| 92 | |
| 93 | static void set_pcu_locks(void) |
| 94 | { |
Patrick Rudolph | ac02857 | 2023-07-14 17:44:33 +0200 | [diff] [blame] | 95 | for (uint32_t socket = 0; socket < CONFIG_MAX_SOCKET; ++socket) { |
| 96 | if (!soc_cpu_is_enabled(socket)) |
| 97 | continue; |
Jonathan Zhang | 3ed903f | 2023-01-25 11:37:27 -0800 | [diff] [blame] | 98 | const uint32_t bus = get_ubox_busno(socket, UNCORE_BUS_1); |
| 99 | |
| 100 | /* configure PCU_CR0_FUN csrs */ |
| 101 | pcu_pci_or_config32(bus, PCU_CR0_FUN, PCU_CR0_P_STATE_LIMITS, |
| 102 | P_STATE_LIMITS_LOCK); |
| 103 | pcu_pci_or_config32(bus, PCU_CR0_FUN, PCU_CR0_PACKAGE_RAPL_LIMIT_UPR, |
| 104 | PKG_PWR_LIM_LOCK_UPR); |
| 105 | pcu_pci_or_config32(bus, PCU_CR0_FUN, PCU_CR0_TURBO_ACTIVATION_RATIO, |
| 106 | TURBO_ACTIVATION_RATIO_LOCK); |
| 107 | |
| 108 | /* configure PCU_CR2_FUN csrs */ |
| 109 | pcu_pci_or_config32(bus, PCU_CR2_FUN, PCU_CR2_DRAM_POWER_INFO_UPR, |
| 110 | DRAM_POWER_INFO_LOCK_UPR); |
| 111 | pcu_pci_or_config32(bus, PCU_CR2_FUN, PCU_CR2_DRAM_PLANE_POWER_LIMIT_UPR, |
| 112 | PP_PWR_LIM_LOCK_UPR); |
| 113 | |
| 114 | /* configure PCU_CR3_FUN csrs */ |
| 115 | pcu_pci_or_config32(bus, PCU_CR3_FUN, PCU_CR3_CONFIG_TDP_CONTROL, TDP_LOCK); |
| 116 | |
| 117 | /* configure PCU_CR6_FUN csrs */ |
| 118 | pcu_pci_or_config32(bus, PCU_CR6_FUN, PCU_CR6_PLATFORM_RAPL_LIMIT_CFG_UPR, |
| 119 | PLT_PWR_LIM_LOCK_UPR); |
| 120 | pcu_pci_or_config32(bus, PCU_CR6_FUN, PCU_CR6_PLATFORM_POWER_INFO_CFG_UPR, |
| 121 | PLT_PWR_INFO_LOCK_UPR); |
| 122 | } |
| 123 | } |
| 124 | |
| 125 | static void chip_final(void *data) |
| 126 | { |
| 127 | /* Lock SBI */ |
| 128 | pci_or_config32(PCH_DEV_P2SB, P2SBC, SBILOCK); |
| 129 | |
| 130 | /* LOCK PAM */ |
| 131 | pci_or_config32(pcidev_path_on_root(PCI_DEVFN(0, 0)), 0x80, 1 << 0); |
| 132 | |
| 133 | set_pcu_locks(); |
| 134 | tco_lockdown(); |
| 135 | |
| 136 | p2sb_hide(); |
| 137 | |
| 138 | /* Accessing xHCI CSR needs to be done after PCI enumeration. */ |
| 139 | lock_oc_cfg(false); |
| 140 | mainboard_override_usb_oc(); |
| 141 | lock_oc_cfg(true); |
| 142 | /* Disable CPU Crashlog to avoid conflict between CPU Crashlog and BMC ACD. */ |
| 143 | disable_cpu_crashlog(); |
| 144 | |
| 145 | set_bios_init_completion(); |
| 146 | } |
| 147 | |
| 148 | static void chip_init(void *data) |
| 149 | { |
| 150 | printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n"); |
| 151 | fsp_silicon_init(); |
| 152 | override_hpet_ioapic_bdf(); |
| 153 | pch_enable_ioapic(); |
| 154 | pch_lock_dmictl(); |
| 155 | p2sb_unhide(); |
| 156 | lock_gpio(false); |
| 157 | mainboard_override_fsp_gpio(); |
| 158 | lock_gpio(true); |
| 159 | } |
| 160 | |
| 161 | struct chip_operations soc_intel_xeon_sp_spr_ops = { |
| 162 | CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev, |
| 163 | .init = chip_init, |
| 164 | .final = chip_final, |
| 165 | }; |
| 166 | |
| 167 | void lock_gpio(bool lock) |
| 168 | { |
| 169 | if (lock) { |
| 170 | pcr_write32(gpio_get_pad_portid(GPPC_B0), PAD_CFG_LOCK_B, 0xffffffff); |
| 171 | pcr_write32(gpio_get_pad_portid(GPP_D0), PAD_CFG_LOCK_D, 0xffffffff); |
| 172 | } else { |
| 173 | pcr_write32(gpio_get_pad_portid(GPPC_B0), PAD_CFG_LOCK_B, 0); |
| 174 | pcr_write32(gpio_get_pad_portid(GPP_D0), PAD_CFG_LOCK_D, 0); |
| 175 | } |
| 176 | } |
| 177 | |
| 178 | /* Root Complex Event Collector */ |
| 179 | static void rcec_init(struct device *dev) |
| 180 | { |
| 181 | /* Set up RCEC EA extended capability, section 7.9.10 of PCIe 5.0 spec */ |
| 182 | const unsigned int rcecea_cap = |
| 183 | pciexp_find_extended_cap(dev, PCIE_EXT_CAP_RCECEA_ID, 0); |
| 184 | if (!rcecea_cap) |
| 185 | return; |
| 186 | |
| 187 | pci_devfn_t ecrc_bdf = PCI_BDF(dev); |
| 188 | uint32_t ecrc_bus = (ecrc_bdf >> 20) & 0xFFF; |
| 189 | uint32_t ecrc_dev = (ecrc_bdf >> 15) & 0x1F; |
| 190 | |
| 191 | /* |
| 192 | * Find all CXL devices, and match them with RCEC. |
| 193 | * With CXL 1.1, the bus# of CXL device (RCiEP) is 1 bigger than |
| 194 | * the bus# of RCEC. |
| 195 | */ |
| 196 | uint32_t ep_bus; |
| 197 | uint8_t i; |
| 198 | for (i = 0; i < pds.num_pds; i++) { |
| 199 | if (pds.pds[i].pd_type == PD_TYPE_PROCESSOR) |
| 200 | continue; |
| 201 | ep_bus = pds.pds[i].device_handle >> 20; |
| 202 | if (ep_bus == ecrc_bus + 1) |
| 203 | break; |
| 204 | } |
| 205 | if (i == pds.num_pds) |
| 206 | return; |
| 207 | |
| 208 | printk(BIOS_DEBUG, "ep_bus: %x, ecrc_dev: %x\n", ep_bus, ecrc_dev); |
| 209 | u32 rcecea_bitmap = 0x1 << ecrc_dev; |
| 210 | u32 rcecea_busnum = (ep_bus << 8) | (ep_bus << 16); |
| 211 | pci_write_config32(dev, rcecea_cap + PCI_RCECEA_BITMAP, rcecea_bitmap); |
| 212 | pci_write_config32(dev, rcecea_cap + PCI_RCECEA_BUSNUM, rcecea_busnum); |
| 213 | } |
| 214 | |
| 215 | #define SPR_IEH 0x0b23 |
| 216 | |
| 217 | static const unsigned short rcec_ids[] = { |
| 218 | SPR_IEH, |
| 219 | 0 |
| 220 | }; |
| 221 | |
| 222 | static struct device_operations rcec_ops = { |
| 223 | .read_resources = pci_dev_read_resources, |
| 224 | .set_resources = pci_dev_set_resources, |
| 225 | .enable_resources = pci_dev_enable_resources, |
| 226 | .init = rcec_init, |
| 227 | .ops_pci = &soc_pci_ops, |
| 228 | }; |
| 229 | |
| 230 | static const struct pci_driver rcec_driver __pci_driver = { |
| 231 | .ops = &rcec_ops, |
| 232 | .vendor = PCI_VID_INTEL, |
| 233 | .devices = rcec_ids, |
| 234 | }; |