Patrick Rudolph | c162131 | 2019-05-28 11:29:29 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; either version 2 of the License, or |
| 7 | * (at your option) any later version. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | */ |
| 14 | |
| 15 | #include <device/device.h> |
| 16 | #include <device/pnp.h> |
| 17 | #include <arch/acpigen.h> |
| 18 | #include <device/pnp_def.h> |
| 19 | #include <console/console.h> |
| 20 | |
| 21 | static void generic_set_resources(struct device *dev) |
| 22 | { |
| 23 | struct resource *res; |
| 24 | |
| 25 | for (res = dev->resource_list; res; res = res->next) { |
| 26 | if (!(res->flags & IORESOURCE_ASSIGNED)) |
| 27 | continue; |
| 28 | |
| 29 | res->flags |= IORESOURCE_STORED; |
| 30 | report_resource_stored(dev, res, ""); |
| 31 | } |
| 32 | } |
| 33 | |
| 34 | static void generic_read_resources(struct device *dev) |
| 35 | { |
| 36 | struct resource *res = new_resource(dev, 0); |
| 37 | res->base = dev->path.pnp.port; |
| 38 | res->size = 2; |
| 39 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 40 | } |
| 41 | |
| 42 | #if CONFIG(HAVE_ACPI_TABLES) |
| 43 | static void generic_ssdt(struct device *dev) |
| 44 | { |
| 45 | const char *scope = acpi_device_scope(dev); |
| 46 | const char *name = acpi_device_name(dev); |
| 47 | |
| 48 | if (!scope || !name) { |
| 49 | printk(BIOS_ERR, "%s: Missing ACPI path/scope\n", |
| 50 | dev_path(dev)); |
| 51 | return; |
| 52 | } |
| 53 | |
| 54 | /* Device */ |
| 55 | acpigen_write_scope(scope); |
| 56 | acpigen_write_device(name); |
| 57 | |
| 58 | printk(BIOS_DEBUG, "%s.%s: %s\n", scope, name, dev_path(dev)); |
| 59 | |
| 60 | acpigen_write_name_string("_HID", "PNP0C02"); |
| 61 | acpigen_write_name_string("_DDN", dev_name(dev)); |
| 62 | |
| 63 | /* OperationRegion("IOID", SYSTEMIO, port, 2) */ |
| 64 | struct opregion opreg = OPREGION("IOID", SYSTEMIO, dev->path.pnp.port, 2); |
| 65 | acpigen_write_opregion(&opreg); |
| 66 | |
| 67 | struct fieldlist l[] = { |
| 68 | FIELDLIST_OFFSET(0), |
| 69 | FIELDLIST_NAMESTR("INDX", 8), |
| 70 | FIELDLIST_NAMESTR("DATA", 8), |
| 71 | }; |
| 72 | |
| 73 | /* Field (IOID, AnyAcc, NoLock, Preserve) |
| 74 | * { |
| 75 | * Offset (0), |
| 76 | * INDX, 8, |
| 77 | * DATA, 8, |
| 78 | * } */ |
| 79 | acpigen_write_field(opreg.name, l, ARRAY_SIZE(l), FIELD_BYTEACC | FIELD_NOLOCK | |
| 80 | FIELD_PRESERVE); |
| 81 | |
| 82 | struct fieldlist i[] = { |
| 83 | FIELDLIST_OFFSET(0x07), |
| 84 | FIELDLIST_NAMESTR("LDN", 8), |
| 85 | FIELDLIST_OFFSET(0x21), |
| 86 | FIELDLIST_NAMESTR("SCF1", 8), |
| 87 | FIELDLIST_NAMESTR("SCF2", 8), |
| 88 | FIELDLIST_NAMESTR("SCF3", 8), |
| 89 | FIELDLIST_NAMESTR("SCF4", 8), |
| 90 | FIELDLIST_NAMESTR("SCF5", 8), |
| 91 | FIELDLIST_NAMESTR("SCF6", 8), |
| 92 | FIELDLIST_NAMESTR("SCF7", 8), |
| 93 | FIELDLIST_OFFSET(0x29), |
| 94 | FIELDLIST_NAMESTR("CKCF", 8), |
| 95 | FIELDLIST_OFFSET(0x2F), |
| 96 | FIELDLIST_NAMESTR("SCFF", 8), |
| 97 | FIELDLIST_OFFSET(0x30), |
| 98 | FIELDLIST_NAMESTR("ACT0", 1), |
| 99 | FIELDLIST_NAMESTR("ACT1", 1), |
| 100 | FIELDLIST_NAMESTR("ACT2", 1), |
| 101 | FIELDLIST_NAMESTR("ACT3", 1), |
| 102 | FIELDLIST_NAMESTR("ACT4", 1), |
| 103 | FIELDLIST_NAMESTR("ACT5", 1), |
| 104 | FIELDLIST_NAMESTR("ACT6", 1), |
| 105 | FIELDLIST_NAMESTR("ACT7", 1), |
| 106 | FIELDLIST_OFFSET(0x60), |
| 107 | FIELDLIST_NAMESTR("IOH0", 8), |
| 108 | FIELDLIST_NAMESTR("IOL0", 8), |
| 109 | FIELDLIST_NAMESTR("IOH1", 8), |
| 110 | FIELDLIST_NAMESTR("IOL1", 8), |
| 111 | FIELDLIST_NAMESTR("IOH2", 8), |
| 112 | FIELDLIST_NAMESTR("IOL2", 8), |
| 113 | FIELDLIST_NAMESTR("IOH3", 8), |
| 114 | FIELDLIST_NAMESTR("IOL3", 8), |
| 115 | FIELDLIST_OFFSET(0x70), |
| 116 | FIELDLIST_NAMESTR("INTR", 4), |
| 117 | FIELDLIST_OFFSET(0x71), |
| 118 | FIELDLIST_NAMESTR("INTT", 2), |
| 119 | FIELDLIST_OFFSET(0x72), |
| 120 | FIELDLIST_NAMESTR("ITR2", 4), |
| 121 | FIELDLIST_OFFSET(0x73), |
| 122 | FIELDLIST_NAMESTR("ITR2", 2), |
| 123 | FIELDLIST_OFFSET(0x74), |
| 124 | FIELDLIST_NAMESTR("DMCH", 8), |
| 125 | FIELDLIST_OFFSET(0xE0), |
| 126 | FIELDLIST_NAMESTR("RGE0", 8), |
| 127 | FIELDLIST_NAMESTR("RGE1", 8), |
| 128 | FIELDLIST_NAMESTR("RGE2", 8), |
| 129 | FIELDLIST_NAMESTR("RGE3", 8), |
| 130 | FIELDLIST_NAMESTR("RGE4", 8), |
| 131 | FIELDLIST_NAMESTR("RGE5", 8), |
| 132 | FIELDLIST_NAMESTR("RGE6", 8), |
| 133 | FIELDLIST_NAMESTR("RGE7", 8), |
| 134 | FIELDLIST_NAMESTR("RGE8", 8), |
| 135 | FIELDLIST_NAMESTR("RGE9", 8), |
| 136 | FIELDLIST_NAMESTR("RGEA", 8), |
| 137 | FIELDLIST_OFFSET(0xF0), |
| 138 | FIELDLIST_NAMESTR("OPT0", 8), |
| 139 | FIELDLIST_NAMESTR("OPT1", 8), |
| 140 | FIELDLIST_NAMESTR("OPT2", 8), |
| 141 | FIELDLIST_NAMESTR("OPT3", 8), |
| 142 | FIELDLIST_NAMESTR("OPT4", 8), |
| 143 | FIELDLIST_NAMESTR("OPT5", 8), |
| 144 | FIELDLIST_NAMESTR("OPT6", 8), |
| 145 | FIELDLIST_NAMESTR("OPT7", 8), |
| 146 | FIELDLIST_NAMESTR("OPT8", 8), |
| 147 | FIELDLIST_NAMESTR("OPT9", 8), |
| 148 | }; |
| 149 | |
| 150 | acpigen_write_indexfield("INDX", "DATA", i, ARRAY_SIZE(i), FIELD_BYTEACC | |
| 151 | FIELD_NOLOCK | FIELD_PRESERVE); |
| 152 | |
| 153 | acpigen_pop_len(); /* Device */ |
| 154 | acpigen_pop_len(); /* Scope */ |
| 155 | } |
| 156 | |
| 157 | static const char *generic_acpi_name(const struct device *dev) |
| 158 | { |
| 159 | return "SIO0"; |
| 160 | } |
| 161 | #endif |
| 162 | |
| 163 | static struct device_operations ops = { |
| 164 | .read_resources = generic_read_resources, |
| 165 | .set_resources = generic_set_resources, |
| 166 | .enable_resources = DEVICE_NOOP, |
| 167 | #if CONFIG(HAVE_ACPI_TABLES) |
| 168 | .acpi_fill_ssdt_generator = generic_ssdt, |
| 169 | .acpi_name = generic_acpi_name, |
| 170 | #endif |
| 171 | }; |
| 172 | |
| 173 | static void enable_dev(struct device *dev) |
| 174 | { |
| 175 | if (dev->path.type != DEVICE_PATH_PNP) |
| 176 | printk(BIOS_ERR, "%s: Unsupported device type\n", dev_path(dev)); |
| 177 | else if (!dev->path.pnp.port) |
| 178 | printk(BIOS_ERR, "%s: Base address not set\n", dev_path(dev)); |
| 179 | else |
| 180 | dev->ops = &ops; |
| 181 | |
| 182 | /* |
| 183 | * Need to call enable_dev() on the devices "behind" the Generic Super I/O. |
| 184 | * coreboot's generic allocator doesn't expect them behind PnP devices. |
| 185 | */ |
| 186 | scan_static_bus(dev); |
| 187 | } |
| 188 | |
| 189 | struct chip_operations superio_common_ops = { |
| 190 | CHIP_NAME("Generic Super I/O") |
| 191 | .enable_dev = enable_dev, |
| 192 | }; |