Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #include <console/console.h> |
| 18 | #include <arch/io.h> |
| 19 | #include <stdint.h> |
| 20 | #include <device/device.h> |
| 21 | #include <device/pci.h> |
| 22 | #include <device/pci_ids.h> |
| 23 | #include <device/hypertransport.h> |
| 24 | #include <stdlib.h> |
| 25 | #include <string.h> |
| 26 | #include <cpu/cpu.h> |
| 27 | #include <boot/tables.h> |
| 28 | #include <arch/acpi.h> |
| 29 | #include <cbmem.h> |
| 30 | #include <northbridge/intel/pineview/pineview.h> |
| 31 | |
| 32 | /* Reserve segments A and B: |
| 33 | * |
| 34 | * 0xa0000 - 0xbffff: legacy VGA |
| 35 | */ |
| 36 | static const int legacy_hole_base_k = 0xa0000 / 1024; |
| 37 | static const int legacy_hole_size_k = 128; |
| 38 | |
| 39 | static void mch_domain_read_resources(device_t dev) |
| 40 | { |
| 41 | u64 tom, touud; |
| 42 | u32 tomk, tolud, uma_sizek = 0, usable_tomk; |
| 43 | u32 pcie_config_base, pcie_config_size; |
| 44 | |
| 45 | pci_domain_read_resources(dev); |
| 46 | |
| 47 | /* Top of Upper Usable DRAM, including remap */ |
Damien Zammit | 02f4764 | 2016-01-18 16:37:41 +1100 | [diff] [blame] | 48 | touud = pci_read_config16(dev, TOUUD); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 49 | touud <<= 20; |
| 50 | |
| 51 | /* Top of Lower Usable DRAM */ |
Damien Zammit | 02f4764 | 2016-01-18 16:37:41 +1100 | [diff] [blame] | 52 | tolud = pci_read_config16(dev, TOLUD) & 0xfff0; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 53 | tolud <<= 16; |
| 54 | |
| 55 | /* Top of Memory - does not account for any UMA */ |
Damien Zammit | 02f4764 | 2016-01-18 16:37:41 +1100 | [diff] [blame] | 56 | tom = pci_read_config16(dev, TOM) & 0x1ff; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 57 | tom <<= 27; |
| 58 | |
| 59 | printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", |
| 60 | touud, tolud, tom); |
| 61 | |
| 62 | tomk = tolud >> 10; |
| 63 | |
| 64 | /* Graphics memory comes next */ |
| 65 | const u16 ggc = pci_read_config16(dev, GGC); |
| 66 | |
| 67 | /* Graphics memory */ |
| 68 | const u32 gms_sizek = decode_igd_memory_size((ggc >> 4) & 0xf); |
| 69 | printk(BIOS_DEBUG, "%uM UMA", gms_sizek >> 10); |
| 70 | tomk -= gms_sizek; |
| 71 | |
| 72 | /* GTT Graphics Stolen Memory Size (GGMS) */ |
| 73 | const u32 gsm_sizek = decode_igd_gtt_size((ggc >> 8) & 0xf); |
| 74 | printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10); |
| 75 | tomk -= gsm_sizek; |
| 76 | |
| 77 | uma_sizek = gms_sizek + gsm_sizek; |
| 78 | |
| 79 | usable_tomk = ALIGN_DOWN(tomk, 64 << 10); |
| 80 | if (tomk - usable_tomk > (16 << 10)) |
| 81 | usable_tomk = tomk; |
| 82 | |
| 83 | printk(BIOS_INFO, "Available memory below 4GB: %uM\n", usable_tomk >> 10); |
| 84 | |
| 85 | /* Report the memory regions */ |
| 86 | ram_resource(dev, 3, 0, legacy_hole_base_k); |
| 87 | ram_resource(dev, 4, legacy_hole_base_k + legacy_hole_size_k, |
| 88 | (usable_tomk - (legacy_hole_base_k + legacy_hole_size_k))); |
| 89 | |
| 90 | mmio_resource(dev, 5, legacy_hole_base_k, |
| 91 | (0xc0000 >> 10) - legacy_hole_base_k); |
| 92 | |
| 93 | /* |
| 94 | * If >= 4GB installed then memory from TOLUD to 4GB |
| 95 | * is remapped above TOM, TOUUD will account for both |
| 96 | */ |
| 97 | touud >>= 10; /* Convert to KB */ |
| 98 | if (touud > 4096 * 1024) { |
| 99 | ram_resource(dev, 6, 4096 * 1024, touud - (4096 * 1024)); |
| 100 | printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", |
| 101 | (touud >> 10) - 4096); |
| 102 | } |
| 103 | |
| 104 | printk(BIOS_DEBUG, "Adding UMA memory area base=0x%llx " |
| 105 | "size=0x%llx\n", ((u64)tomk) << 10, ((u64)uma_sizek) << 10); |
| 106 | /* Don't use uma_resource() as our UMA touches the PCI hole. */ |
| 107 | fixed_mem_resource(dev, 7, tomk, uma_sizek, IORESOURCE_RESERVE); |
| 108 | |
| 109 | if (decode_pciebar(&pcie_config_base, &pcie_config_size)) { |
| 110 | printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " |
| 111 | "size=0x%x\n", pcie_config_base, pcie_config_size); |
| 112 | fixed_mem_resource(dev, 8, pcie_config_base >> 10, |
| 113 | pcie_config_size >> 10, IORESOURCE_RESERVE); |
| 114 | } |
| 115 | |
| 116 | set_top_of_ram(tomk << 10); |
| 117 | } |
| 118 | |
| 119 | static void mch_domain_set_resources(device_t dev) |
| 120 | { |
| 121 | struct resource *resource; |
| 122 | int i; |
| 123 | |
| 124 | for (i = 3; i < 9; ++i) { |
| 125 | /* Report read resources. */ |
| 126 | resource = probe_resource(dev, i); |
| 127 | if (resource) |
| 128 | report_resource_stored(dev, resource, ""); |
| 129 | } |
| 130 | |
| 131 | assign_resources(dev->link_list); |
| 132 | } |
| 133 | |
| 134 | static void mch_domain_init(device_t dev) |
| 135 | { |
| 136 | u32 reg32; |
| 137 | |
| 138 | /* Enable SERR */ |
| 139 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 140 | reg32 |= PCI_COMMAND_SERR; |
| 141 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 142 | } |
| 143 | |
| 144 | static struct device_operations pci_domain_ops = { |
| 145 | .read_resources = mch_domain_read_resources, |
| 146 | .set_resources = mch_domain_set_resources, |
| 147 | .enable_resources = NULL, |
| 148 | .init = mch_domain_init, |
| 149 | .scan_bus = pci_domain_scan_bus, |
| 150 | .ops_pci_bus = pci_bus_default_ops, |
| 151 | }; |
| 152 | |
| 153 | static void cpu_bus_init(device_t dev) |
| 154 | { |
| 155 | initialize_cpus(dev->link_list); |
| 156 | } |
| 157 | |
| 158 | static struct device_operations cpu_bus_ops = { |
| 159 | .read_resources = DEVICE_NOOP, |
| 160 | .set_resources = DEVICE_NOOP, |
| 161 | .enable_resources = DEVICE_NOOP, |
| 162 | .init = cpu_bus_init, |
| 163 | .scan_bus = 0, |
| 164 | }; |
| 165 | |
| 166 | |
| 167 | static void enable_dev(device_t dev) |
| 168 | { |
| 169 | /* Set the operations if it is a special bus type */ |
| 170 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 171 | dev->ops = &pci_domain_ops; |
| 172 | #if CONFIG_HAVE_ACPI_RESUME |
| 173 | switch (pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), /*D0F0_SKPD*/0xdc)) { |
| 174 | case SKPAD_NORMAL_BOOT_MAGIC: |
| 175 | printk(BIOS_DEBUG, "Normal boot.\n"); |
| 176 | acpi_slp_type=0; |
| 177 | break; |
| 178 | case SKPAD_ACPI_S3_MAGIC: |
| 179 | printk(BIOS_DEBUG, "S3 Resume.\n"); |
| 180 | acpi_slp_type=3; |
| 181 | break; |
| 182 | default: |
| 183 | printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); |
| 184 | acpi_slp_type=0; |
| 185 | break; |
| 186 | } |
| 187 | #endif |
| 188 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 189 | dev->ops = &cpu_bus_ops; |
| 190 | } |
| 191 | } |
| 192 | |
| 193 | static void pineview_init(void *const chip_info) |
| 194 | { |
| 195 | int dev, fn; |
| 196 | |
| 197 | struct device *const d0f0 = dev_find_slot(0, 0); |
| 198 | |
| 199 | const struct { |
| 200 | u8 fn; |
| 201 | u8 bitbase; |
| 202 | } intfunc[] = { |
| 203 | {0, 0}, |
| 204 | {0, 1}, /* PEG */ |
| 205 | {1, 3}, /* IGD */ |
| 206 | {3, 6}, /* ME */ |
| 207 | }; |
| 208 | |
| 209 | /* Hide internal functions based on devicetree info. */ |
| 210 | for (dev = 3; dev > 0; --dev) { |
| 211 | for (fn = intfunc[dev].fn; fn >= 0; --fn) { |
| 212 | const struct device *const d = |
| 213 | dev_find_slot(0, PCI_DEVFN(dev, fn)); |
| 214 | if (!d || d->enabled) continue; |
| 215 | const u32 deven = pci_read_config32(d0f0, DEVEN); |
| 216 | pci_write_config32(d0f0, DEVEN, deven |
| 217 | & ~(1 << (intfunc[dev].bitbase + fn))); |
| 218 | } |
| 219 | } |
| 220 | |
| 221 | const u32 deven = pci_read_config32(d0f0, DEVEN); |
| 222 | if (!(deven & (0xf << 6))) |
| 223 | pci_write_config32(d0f0, DEVEN, deven & ~(1 << 14)); |
| 224 | } |
| 225 | |
| 226 | struct chip_operations northbridge_intel_pineview_ops = { |
| 227 | CHIP_NAME("Intel Pineview Northbridge") |
| 228 | .enable_dev = enable_dev, |
| 229 | .init = pineview_init, |
| 230 | }; |