blob: 164bd8e4654d63e419d2014234c229554eb0f350 [file] [log] [blame]
Patrick Georgi406313d2015-07-20 22:01:32 +02001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2008-2009 coresystems GmbH
5 * Copyright (C) 2015 Google Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.
19 */
20
21#include <arch/io.h>
22#include <console/console.h>
23#include <cpu/x86/smm.h>
24#include <elog.h>
25#include <ec/google/chromeec/ec.h>
26#include <soc/iomap.h>
27#include <soc/nvs.h>
28#include <soc/pm.h>
29#include <soc/smm.h>
30#include "ec.h"
31
32int mainboard_io_trap_handler(int smif)
33{
34 switch (smif) {
35 case 0x99:
36 printk(BIOS_DEBUG, "Sample\n");
37 smm_get_gnvs()->smif = 0;
38 break;
39 default:
40 return 0;
41 }
42
43 /* On success, the IO Trap Handler returns 0
44 * On failure, the IO Trap Handler returns a value != 0
45 *
46 * For now, we force the return value to 0 and log all traps to
47 * see what's going on.
48 */
49 return 1;
50}
51
52static u8 mainboard_smi_ec(void)
53{
54 u8 cmd = 0;
55#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
56 u32 pm1_cnt;
57 cmd = google_chromeec_get_event();
58
59 /* Log this event */
60 if (IS_ENABLED(CONFIG_ELOG_GSMI) && cmd)
61 elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
62
63 switch (cmd) {
64 case EC_HOST_EVENT_LID_CLOSED:
65 printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
66
67 /* Go to S5 */
68 pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
69 pm1_cnt |= (0xf << 10);
70 outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
71 break;
72 }
73#endif
74 return cmd;
75}
76
77/* gpi_sts is GPIO 47:32 */
78void mainboard_smi_gpi(u32 gpi_sts)
79{
80 if (gpi_sts & (1 << EC_SMI_GPI)) {
81 /* Process all pending events */
82 while (mainboard_smi_ec() != 0)
83 ;
84 }
85}
86
87void mainboard_smi_sleep(u8 slp_typ)
88{
89#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
90 /* Disable USB charging if required */
91 switch (slp_typ) {
92 case 3:
93 if (smm_get_gnvs()->s3u0 == 0) {
94 google_chromeec_set_usb_charge_mode(
95 0, USB_CHARGE_MODE_DISABLED);
96 google_chromeec_set_usb_charge_mode(
97 1, USB_CHARGE_MODE_DISABLED);
98 }
99
100 /* Enable wake events */
101 google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
102 break;
103 case 5:
104 if (smm_get_gnvs()->s5u0 == 0) {
105 google_chromeec_set_usb_charge_mode(
106 0, USB_CHARGE_MODE_DISABLED);
107 google_chromeec_set_usb_charge_mode(
108 1, USB_CHARGE_MODE_DISABLED);
109 }
110
111 /* Enable wake events */
112 google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
113 break;
114 }
115
116 /* Disable SCI and SMI events */
117 google_chromeec_set_smi_mask(0);
118 google_chromeec_set_sci_mask(0);
119
120 /* Clear pending events that may trigger immediate wake */
121 while (google_chromeec_get_event() != 0)
122 ;
123#endif
124}
125
126int mainboard_smi_apmc(u8 apmc)
127{
128#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
129 switch (apmc) {
130 case APM_CNT_ACPI_ENABLE:
131 google_chromeec_set_smi_mask(0);
132 /* Clear all pending events */
133 while (google_chromeec_get_event() != 0)
134 ;
135 google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
136 break;
137 case APM_CNT_ACPI_DISABLE:
138 google_chromeec_set_sci_mask(0);
139 /* Clear all pending events */
140 while (google_chromeec_get_event() != 0)
141 ;
142 google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
143 break;
144 }
145#endif
146 return 0;
147}