Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Chromium OS Authors |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <arch/io.h> |
| 17 | #include <console/console.h> |
Kyösti Mälkki | ab56b3b | 2013-11-28 16:44:51 +0200 | [diff] [blame] | 18 | #include <bootmode.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 19 | #include <delay.h> |
Vladimir Serbinenko | f2e206a | 2014-02-23 00:13:56 +0100 | [diff] [blame] | 20 | #include <string.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 21 | #include <device/device.h> |
| 22 | #include <device/pci.h> |
| 23 | #include <device/pci_ids.h> |
Ronald G. Minnich | 69efaa0 | 2013-02-26 10:07:40 -0800 | [diff] [blame] | 24 | #include <device/pci_ops.h> |
| 25 | #include <cpu/x86/msr.h> |
| 26 | #include <cpu/x86/mtrr.h> |
Nico Huber | 1822816 | 2017-06-08 16:31:57 +0200 | [diff] [blame^] | 27 | #include <drivers/intel/gma/libgfxinit.h> |
Patrick Rudolph | 281ccca | 2017-04-12 16:55:32 +0200 | [diff] [blame] | 28 | #include <southbridge/intel/bd82x6x/nvs.h> |
Matt DeVillier | ebe08e0 | 2017-07-14 13:28:42 -0500 | [diff] [blame] | 29 | #include <drivers/intel/gma/opregion.h> |
Patrick Rudolph | 281ccca | 2017-04-12 16:55:32 +0200 | [diff] [blame] | 30 | #include <cbmem.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 31 | |
| 32 | #include "chip.h" |
| 33 | #include "sandybridge.h" |
Patrick Rudolph | 45a0dbc | 2017-03-30 17:07:42 +0200 | [diff] [blame] | 34 | #include "gma.h" |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 35 | |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 36 | struct gt_powermeter { |
| 37 | u16 reg; |
| 38 | u32 value; |
| 39 | }; |
| 40 | |
Stefan Reinauer | 4c8027a | 2012-09-07 10:53:56 -0700 | [diff] [blame] | 41 | static const struct gt_powermeter snb_pm_gt1[] = { |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 42 | { 0xa200, 0xcc000000 }, |
| 43 | { 0xa204, 0x07000040 }, |
| 44 | { 0xa208, 0x0000fe00 }, |
| 45 | { 0xa20c, 0x00000000 }, |
| 46 | { 0xa210, 0x17000000 }, |
| 47 | { 0xa214, 0x00000021 }, |
| 48 | { 0xa218, 0x0817fe19 }, |
| 49 | { 0xa21c, 0x00000000 }, |
| 50 | { 0xa220, 0x00000000 }, |
| 51 | { 0xa224, 0xcc000000 }, |
| 52 | { 0xa228, 0x07000040 }, |
| 53 | { 0xa22c, 0x0000fe00 }, |
| 54 | { 0xa230, 0x00000000 }, |
| 55 | { 0xa234, 0x17000000 }, |
| 56 | { 0xa238, 0x00000021 }, |
| 57 | { 0xa23c, 0x0817fe19 }, |
| 58 | { 0xa240, 0x00000000 }, |
| 59 | { 0xa244, 0x00000000 }, |
| 60 | { 0xa248, 0x8000421e }, |
| 61 | { 0 } |
| 62 | }; |
| 63 | |
Stefan Reinauer | 4c8027a | 2012-09-07 10:53:56 -0700 | [diff] [blame] | 64 | static const struct gt_powermeter snb_pm_gt2[] = { |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 65 | { 0xa200, 0x330000a6 }, |
| 66 | { 0xa204, 0x402d0031 }, |
| 67 | { 0xa208, 0x00165f83 }, |
| 68 | { 0xa20c, 0xf1000000 }, |
| 69 | { 0xa210, 0x00000000 }, |
| 70 | { 0xa214, 0x00160016 }, |
| 71 | { 0xa218, 0x002a002b }, |
| 72 | { 0xa21c, 0x00000000 }, |
| 73 | { 0xa220, 0x00000000 }, |
| 74 | { 0xa224, 0x330000a6 }, |
| 75 | { 0xa228, 0x402d0031 }, |
| 76 | { 0xa22c, 0x00165f83 }, |
| 77 | { 0xa230, 0xf1000000 }, |
| 78 | { 0xa234, 0x00000000 }, |
| 79 | { 0xa238, 0x00160016 }, |
| 80 | { 0xa23c, 0x002a002b }, |
| 81 | { 0xa240, 0x00000000 }, |
| 82 | { 0xa244, 0x00000000 }, |
| 83 | { 0xa248, 0x8000421e }, |
| 84 | { 0 } |
| 85 | }; |
| 86 | |
Stefan Reinauer | 4c8027a | 2012-09-07 10:53:56 -0700 | [diff] [blame] | 87 | static const struct gt_powermeter ivb_pm_gt1[] = { |
Duncan Laurie | 8508cff | 2012-04-12 16:02:43 -0700 | [diff] [blame] | 88 | { 0xa800, 0x00000000 }, |
| 89 | { 0xa804, 0x00021c00 }, |
| 90 | { 0xa808, 0x00000403 }, |
| 91 | { 0xa80c, 0x02001700 }, |
| 92 | { 0xa810, 0x05000200 }, |
| 93 | { 0xa814, 0x00000000 }, |
| 94 | { 0xa818, 0x00690500 }, |
| 95 | { 0xa81c, 0x0000007f }, |
| 96 | { 0xa820, 0x01002501 }, |
| 97 | { 0xa824, 0x00000300 }, |
| 98 | { 0xa828, 0x01000331 }, |
| 99 | { 0xa82c, 0x0000000c }, |
| 100 | { 0xa830, 0x00010016 }, |
| 101 | { 0xa834, 0x01100101 }, |
| 102 | { 0xa838, 0x00010103 }, |
| 103 | { 0xa83c, 0x00041300 }, |
| 104 | { 0xa840, 0x00000b30 }, |
| 105 | { 0xa844, 0x00000000 }, |
| 106 | { 0xa848, 0x7f000000 }, |
| 107 | { 0xa84c, 0x05000008 }, |
| 108 | { 0xa850, 0x00000001 }, |
| 109 | { 0xa854, 0x00000004 }, |
| 110 | { 0xa858, 0x00000007 }, |
| 111 | { 0xa85c, 0x00000000 }, |
| 112 | { 0xa860, 0x00010000 }, |
| 113 | { 0xa248, 0x0000221e }, |
| 114 | { 0xa900, 0x00000000 }, |
| 115 | { 0xa904, 0x00001c00 }, |
| 116 | { 0xa908, 0x00000000 }, |
| 117 | { 0xa90c, 0x06000000 }, |
| 118 | { 0xa910, 0x09000200 }, |
| 119 | { 0xa914, 0x00000000 }, |
| 120 | { 0xa918, 0x00590000 }, |
| 121 | { 0xa91c, 0x00000000 }, |
| 122 | { 0xa920, 0x04002501 }, |
| 123 | { 0xa924, 0x00000100 }, |
| 124 | { 0xa928, 0x03000410 }, |
| 125 | { 0xa92c, 0x00000000 }, |
| 126 | { 0xa930, 0x00020000 }, |
| 127 | { 0xa934, 0x02070106 }, |
| 128 | { 0xa938, 0x00010100 }, |
| 129 | { 0xa93c, 0x00401c00 }, |
| 130 | { 0xa940, 0x00000000 }, |
| 131 | { 0xa944, 0x00000000 }, |
| 132 | { 0xa948, 0x10000e00 }, |
| 133 | { 0xa94c, 0x02000004 }, |
| 134 | { 0xa950, 0x00000001 }, |
| 135 | { 0xa954, 0x00000004 }, |
| 136 | { 0xa960, 0x00060000 }, |
| 137 | { 0xaa3c, 0x00001c00 }, |
| 138 | { 0xaa54, 0x00000004 }, |
| 139 | { 0xaa60, 0x00060000 }, |
| 140 | { 0 } |
| 141 | }; |
| 142 | |
Stefan Reinauer | 4c8027a | 2012-09-07 10:53:56 -0700 | [diff] [blame] | 143 | static const struct gt_powermeter ivb_pm_gt2_17w[] = { |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 144 | { 0xa800, 0x20000000 }, |
| 145 | { 0xa804, 0x000e3800 }, |
| 146 | { 0xa808, 0x00000806 }, |
| 147 | { 0xa80c, 0x0c002f00 }, |
| 148 | { 0xa810, 0x0c000800 }, |
| 149 | { 0xa814, 0x00000000 }, |
| 150 | { 0xa818, 0x00d20d00 }, |
| 151 | { 0xa81c, 0x000000ff }, |
| 152 | { 0xa820, 0x03004b02 }, |
| 153 | { 0xa824, 0x00000600 }, |
| 154 | { 0xa828, 0x07000773 }, |
| 155 | { 0xa82c, 0x00000000 }, |
| 156 | { 0xa830, 0x00020032 }, |
| 157 | { 0xa834, 0x1520040d }, |
| 158 | { 0xa838, 0x00020105 }, |
| 159 | { 0xa83c, 0x00083700 }, |
| 160 | { 0xa840, 0x000016ff }, |
| 161 | { 0xa844, 0x00000000 }, |
| 162 | { 0xa848, 0xff000000 }, |
| 163 | { 0xa84c, 0x0a000010 }, |
Duncan Laurie | 8508cff | 2012-04-12 16:02:43 -0700 | [diff] [blame] | 164 | { 0xa850, 0x00000002 }, |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 165 | { 0xa854, 0x00000008 }, |
Duncan Laurie | 8508cff | 2012-04-12 16:02:43 -0700 | [diff] [blame] | 166 | { 0xa858, 0x0000000f }, |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 167 | { 0xa85c, 0x00000000 }, |
| 168 | { 0xa860, 0x00020000 }, |
| 169 | { 0xa248, 0x0000221e }, |
| 170 | { 0xa900, 0x00000000 }, |
| 171 | { 0xa904, 0x00003800 }, |
| 172 | { 0xa908, 0x00000000 }, |
| 173 | { 0xa90c, 0x0c000000 }, |
Duncan Laurie | 8508cff | 2012-04-12 16:02:43 -0700 | [diff] [blame] | 174 | { 0xa910, 0x12000800 }, |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 175 | { 0xa914, 0x00000000 }, |
| 176 | { 0xa918, 0x00b20000 }, |
| 177 | { 0xa91c, 0x00000000 }, |
| 178 | { 0xa920, 0x08004b02 }, |
Duncan Laurie | 8508cff | 2012-04-12 16:02:43 -0700 | [diff] [blame] | 179 | { 0xa924, 0x00000300 }, |
| 180 | { 0xa928, 0x01000820 }, |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 181 | { 0xa92c, 0x00000000 }, |
| 182 | { 0xa930, 0x00030000 }, |
Duncan Laurie | 8508cff | 2012-04-12 16:02:43 -0700 | [diff] [blame] | 183 | { 0xa934, 0x15150406 }, |
| 184 | { 0xa938, 0x00020300 }, |
| 185 | { 0xa93c, 0x00903900 }, |
| 186 | { 0xa940, 0x00000000 }, |
| 187 | { 0xa944, 0x00000000 }, |
| 188 | { 0xa948, 0x20001b00 }, |
| 189 | { 0xa94c, 0x0a000010 }, |
| 190 | { 0xa950, 0x00000000 }, |
| 191 | { 0xa954, 0x00000008 }, |
| 192 | { 0xa960, 0x00110000 }, |
| 193 | { 0xaa3c, 0x00003900 }, |
| 194 | { 0xaa54, 0x00000008 }, |
| 195 | { 0xaa60, 0x00110000 }, |
| 196 | { 0 } |
| 197 | }; |
| 198 | |
Stefan Reinauer | 4c8027a | 2012-09-07 10:53:56 -0700 | [diff] [blame] | 199 | static const struct gt_powermeter ivb_pm_gt2_35w[] = { |
Duncan Laurie | 8508cff | 2012-04-12 16:02:43 -0700 | [diff] [blame] | 200 | { 0xa800, 0x00000000 }, |
| 201 | { 0xa804, 0x00030400 }, |
| 202 | { 0xa808, 0x00000806 }, |
| 203 | { 0xa80c, 0x0c002f00 }, |
| 204 | { 0xa810, 0x0c000300 }, |
| 205 | { 0xa814, 0x00000000 }, |
| 206 | { 0xa818, 0x00d20d00 }, |
| 207 | { 0xa81c, 0x000000ff }, |
| 208 | { 0xa820, 0x03004b02 }, |
| 209 | { 0xa824, 0x00000600 }, |
| 210 | { 0xa828, 0x07000773 }, |
| 211 | { 0xa82c, 0x00000000 }, |
| 212 | { 0xa830, 0x00020032 }, |
| 213 | { 0xa834, 0x1520040d }, |
| 214 | { 0xa838, 0x00020105 }, |
| 215 | { 0xa83c, 0x00083700 }, |
| 216 | { 0xa840, 0x000016ff }, |
| 217 | { 0xa844, 0x00000000 }, |
| 218 | { 0xa848, 0xff000000 }, |
| 219 | { 0xa84c, 0x0a000010 }, |
| 220 | { 0xa850, 0x00000001 }, |
| 221 | { 0xa854, 0x00000008 }, |
| 222 | { 0xa858, 0x00000008 }, |
| 223 | { 0xa85c, 0x00000000 }, |
| 224 | { 0xa860, 0x00020000 }, |
| 225 | { 0xa248, 0x0000221e }, |
| 226 | { 0xa900, 0x00000000 }, |
| 227 | { 0xa904, 0x00003800 }, |
| 228 | { 0xa908, 0x00000000 }, |
| 229 | { 0xa90c, 0x0c000000 }, |
| 230 | { 0xa910, 0x12000800 }, |
| 231 | { 0xa914, 0x00000000 }, |
| 232 | { 0xa918, 0x00b20000 }, |
| 233 | { 0xa91c, 0x00000000 }, |
| 234 | { 0xa920, 0x08004b02 }, |
| 235 | { 0xa924, 0x00000300 }, |
| 236 | { 0xa928, 0x01000820 }, |
| 237 | { 0xa92c, 0x00000000 }, |
| 238 | { 0xa930, 0x00030000 }, |
| 239 | { 0xa934, 0x15150406 }, |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 240 | { 0xa938, 0x00020300 }, |
| 241 | { 0xa93c, 0x00903900 }, |
| 242 | { 0xa940, 0x00000000 }, |
| 243 | { 0xa944, 0x00000000 }, |
| 244 | { 0xa948, 0x20001b00 }, |
| 245 | { 0xa94c, 0x0a000010 }, |
| 246 | { 0xa950, 0x00000000 }, |
| 247 | { 0xa954, 0x00000008 }, |
| 248 | { 0xa960, 0x00110000 }, |
| 249 | { 0xaa3c, 0x00003900 }, |
| 250 | { 0xaa54, 0x00000008 }, |
| 251 | { 0xaa60, 0x00110000 }, |
| 252 | { 0 } |
| 253 | }; |
| 254 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 255 | /* some vga option roms are used for several chipsets but they only have one |
| 256 | * PCI ID in their header. If we encounter such an option rom, we need to do |
Martin Roth | 128c104 | 2016-11-18 09:29:03 -0700 | [diff] [blame] | 257 | * the mapping ourselves |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 258 | */ |
| 259 | |
| 260 | u32 map_oprom_vendev(u32 vendev) |
| 261 | { |
Nico Huber | 23b93dd | 2017-07-29 01:46:23 +0200 | [diff] [blame] | 262 | u32 new_vendev = vendev; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 263 | |
| 264 | switch (vendev) { |
Nico Huber | 23b93dd | 2017-07-29 01:46:23 +0200 | [diff] [blame] | 265 | case 0x80860102: /* SNB GT1 Desktop */ |
| 266 | case 0x8086010a: /* SNB GT1 Server */ |
| 267 | case 0x80860112: /* SNB GT2 Desktop */ |
| 268 | case 0x80860116: /* SNB GT2 Mobile */ |
| 269 | case 0x80860122: /* SNB GT2 Desktop >=1.3GHz */ |
| 270 | case 0x80860126: /* SNB GT2 Mobile >=1.3GHz */ |
| 271 | case 0x80860152: /* IVB GT1 Desktop */ |
| 272 | case 0x80860156: /* IVB GT1 Mobile */ |
| 273 | case 0x80860162: /* IVB GT2 Desktop */ |
| 274 | case 0x80860166: /* IVB GT2 Mobile */ |
Vagiz Trakhanov | 1dd448c | 2017-09-28 14:42:11 +0000 | [diff] [blame] | 275 | case 0x8086016a: /* IVB GT2 Server */ |
Nico Huber | 23b93dd | 2017-07-29 01:46:23 +0200 | [diff] [blame] | 276 | new_vendev = 0x80860106;/* SNB GT1 Mobile */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 277 | break; |
| 278 | } |
| 279 | |
| 280 | return new_vendev; |
| 281 | } |
| 282 | |
| 283 | static struct resource *gtt_res = NULL; |
| 284 | |
Vladimir Serbinenko | a71bdc3 | 2014-08-30 00:35:39 +0200 | [diff] [blame] | 285 | u32 gtt_read(u32 reg) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 286 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 287 | return read32(res2mmio(gtt_res, reg, 0)); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 288 | } |
| 289 | |
Vladimir Serbinenko | a71bdc3 | 2014-08-30 00:35:39 +0200 | [diff] [blame] | 290 | void gtt_write(u32 reg, u32 data) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 291 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 292 | write32(res2mmio(gtt_res, reg, 0), data); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 293 | } |
| 294 | |
Stefan Reinauer | 4c8027a | 2012-09-07 10:53:56 -0700 | [diff] [blame] | 295 | static inline void gtt_write_powermeter(const struct gt_powermeter *pm) |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 296 | { |
| 297 | for (; pm && pm->reg; pm++) |
| 298 | gtt_write(pm->reg, pm->value); |
| 299 | } |
| 300 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 301 | #define GTT_RETRY 1000 |
Vladimir Serbinenko | a71bdc3 | 2014-08-30 00:35:39 +0200 | [diff] [blame] | 302 | int gtt_poll(u32 reg, u32 mask, u32 value) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 303 | { |
| 304 | unsigned try = GTT_RETRY; |
| 305 | u32 data; |
| 306 | |
| 307 | while (try--) { |
| 308 | data = gtt_read(reg); |
| 309 | if ((data & mask) == value) |
| 310 | return 1; |
| 311 | udelay(10); |
| 312 | } |
| 313 | |
| 314 | printk(BIOS_ERR, "GT init timeout\n"); |
| 315 | return 0; |
| 316 | } |
| 317 | |
Patrick Rudolph | 19c2ad8 | 2017-06-30 14:52:01 +0200 | [diff] [blame] | 318 | uintptr_t gma_get_gnvs_aslb(const void *gnvs) |
| 319 | { |
| 320 | const global_nvs_t *gnvs_ptr = gnvs; |
| 321 | return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); |
| 322 | } |
| 323 | |
| 324 | void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) |
| 325 | { |
| 326 | global_nvs_t *gnvs_ptr = gnvs; |
| 327 | if (gnvs_ptr) |
| 328 | gnvs_ptr->aslb = aslb; |
| 329 | } |
| 330 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 331 | static void gma_pm_init_pre_vbios(struct device *dev) |
| 332 | { |
| 333 | u32 reg32; |
| 334 | |
| 335 | printk(BIOS_DEBUG, "GT Power Management Init\n"); |
| 336 | |
| 337 | gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 338 | if (!gtt_res || !gtt_res->base) |
| 339 | return; |
| 340 | |
| 341 | if (bridge_silicon_revision() < IVB_STEP_C0) { |
| 342 | /* 1: Enable force wake */ |
| 343 | gtt_write(0xa18c, 0x00000001); |
Duncan Laurie | da83a5f | 2012-05-25 10:04:17 -0700 | [diff] [blame] | 344 | gtt_poll(0x130090, (1 << 0), (1 << 0)); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 345 | } else { |
| 346 | gtt_write(0xa180, 1 << 5); |
| 347 | gtt_write(0xa188, 0xffff0001); |
Duncan Laurie | da83a5f | 2012-05-25 10:04:17 -0700 | [diff] [blame] | 348 | gtt_poll(0x130040, (1 << 0), (1 << 0)); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 349 | } |
| 350 | |
| 351 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { |
| 352 | /* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */ |
| 353 | reg32 = gtt_read(0x42004); |
| 354 | reg32 |= (1 << 14) | (1 << 15); |
| 355 | gtt_write(0x42004, reg32); |
| 356 | } |
| 357 | |
| 358 | if (bridge_silicon_revision() >= IVB_STEP_A0) { |
| 359 | /* Display Reset Acknowledge Settings */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 360 | reg32 = gtt_read(0x45010); |
| 361 | reg32 |= (1 << 1) | (1 << 0); |
| 362 | gtt_write(0x45010, reg32); |
| 363 | } |
| 364 | |
| 365 | /* 2: Get GT SKU from GTT+0x911c[13] */ |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 366 | reg32 = gtt_read(0x911c); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 367 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 368 | if (reg32 & (1 << 13)) { |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 369 | printk(BIOS_DEBUG, "SNB GT1 Power Meter Weights\n"); |
| 370 | gtt_write_powermeter(snb_pm_gt1); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 371 | } else { |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 372 | printk(BIOS_DEBUG, "SNB GT2 Power Meter Weights\n"); |
| 373 | gtt_write_powermeter(snb_pm_gt2); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 374 | } |
| 375 | } else { |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 376 | u32 unit = MCHBAR32(0x5938) & 0xf; |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 377 | |
Duncan Laurie | 8508cff | 2012-04-12 16:02:43 -0700 | [diff] [blame] | 378 | if (reg32 & (1 << 13)) { |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 379 | /* GT1 SKU */ |
| 380 | printk(BIOS_DEBUG, "IVB GT1 Power Meter Weights\n"); |
| 381 | gtt_write_powermeter(ivb_pm_gt1); |
Duncan Laurie | 8508cff | 2012-04-12 16:02:43 -0700 | [diff] [blame] | 382 | } else { |
| 383 | /* GT2 SKU */ |
| 384 | u32 tdp = MCHBAR32(0x5930) & 0x7fff; |
| 385 | tdp /= (1 << unit); |
| 386 | |
| 387 | if (tdp <= 17) { |
| 388 | /* <=17W ULV */ |
| 389 | printk(BIOS_DEBUG, "IVB GT2 17W " |
| 390 | "Power Meter Weights\n"); |
| 391 | gtt_write_powermeter(ivb_pm_gt2_17w); |
| 392 | } else if ((tdp >= 25) && (tdp <= 35)) { |
| 393 | /* 25W-35W */ |
Duncan Laurie | da83a5f | 2012-05-25 10:04:17 -0700 | [diff] [blame] | 394 | printk(BIOS_DEBUG, "IVB GT2 25W-35W " |
Duncan Laurie | 8508cff | 2012-04-12 16:02:43 -0700 | [diff] [blame] | 395 | "Power Meter Weights\n"); |
| 396 | gtt_write_powermeter(ivb_pm_gt2_35w); |
| 397 | } else { |
| 398 | /* All others */ |
| 399 | printk(BIOS_DEBUG, "IVB GT2 35W " |
| 400 | "Power Meter Weights\n"); |
| 401 | gtt_write_powermeter(ivb_pm_gt2_35w); |
| 402 | } |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 403 | } |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 404 | } |
| 405 | |
| 406 | /* 3: Gear ratio map */ |
| 407 | gtt_write(0xa004, 0x00000010); |
| 408 | |
| 409 | /* 4: GFXPAUSE */ |
| 410 | gtt_write(0xa000, 0x00070020); |
| 411 | |
| 412 | /* 5: Dynamic EU trip control */ |
| 413 | gtt_write(0xa080, 0x00000004); |
| 414 | |
| 415 | /* 6: ECO bits */ |
| 416 | reg32 = gtt_read(0xa180); |
| 417 | reg32 |= (1 << 26) | (1 << 31); |
| 418 | /* (bit 20=1 for SNB step D1+ / IVB A0+) */ |
| 419 | if (bridge_silicon_revision() >= SNB_STEP_D1) |
| 420 | reg32 |= (1 << 20); |
| 421 | gtt_write(0xa180, reg32); |
| 422 | |
| 423 | /* 6a: for SnB step D2+ only */ |
| 424 | if (((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) && |
| 425 | (bridge_silicon_revision() >= SNB_STEP_D2)) { |
| 426 | reg32 = gtt_read(0x9400); |
| 427 | reg32 |= (1 << 7); |
| 428 | gtt_write(0x9400, reg32); |
| 429 | |
| 430 | reg32 = gtt_read(0x941c); |
| 431 | reg32 &= 0xf; |
| 432 | reg32 |= (1 << 1); |
| 433 | gtt_write(0x941c, reg32); |
Duncan Laurie | da83a5f | 2012-05-25 10:04:17 -0700 | [diff] [blame] | 434 | gtt_poll(0x941c, (1 << 1), (0 << 1)); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 435 | } |
| 436 | |
| 437 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { |
| 438 | reg32 = gtt_read(0x907c); |
| 439 | reg32 |= (1 << 16); |
| 440 | gtt_write(0x907c, reg32); |
| 441 | |
| 442 | /* 6b: Clocking reset controls */ |
| 443 | gtt_write(0x9424, 0x00000001); |
| 444 | } else { |
| 445 | /* 6b: Clocking reset controls */ |
| 446 | gtt_write(0x9424, 0x00000000); |
| 447 | } |
| 448 | |
| 449 | /* 7 */ |
Duncan Laurie | da83a5f | 2012-05-25 10:04:17 -0700 | [diff] [blame] | 450 | if (gtt_poll(0x138124, (1 << 31), (0 << 31))) { |
| 451 | gtt_write(0x138128, 0x00000029); /* Mailbox Data */ |
| 452 | gtt_write(0x138124, 0x80000004); /* Mailbox Cmd for RC6 VID */ |
| 453 | if (gtt_poll(0x138124, (1 << 31), (0 << 31))) |
| 454 | gtt_write(0x138124, 0x8000000a); |
| 455 | gtt_poll(0x138124, (1 << 31), (0 << 31)); |
| 456 | } |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 457 | |
| 458 | /* 8 */ |
| 459 | gtt_write(0xa090, 0x00000000); /* RC Control */ |
| 460 | gtt_write(0xa098, 0x03e80000); /* RC1e Wake Rate Limit */ |
| 461 | gtt_write(0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */ |
| 462 | gtt_write(0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */ |
| 463 | gtt_write(0xa0a8, 0x0001e848); /* RC Evaluation Interval */ |
| 464 | gtt_write(0xa0ac, 0x00000019); /* RC Idle Hysteresis */ |
| 465 | |
| 466 | /* 9 */ |
| 467 | gtt_write(0x2054, 0x0000000a); /* Render Idle Max Count */ |
| 468 | gtt_write(0x12054,0x0000000a); /* Video Idle Max Count */ |
| 469 | gtt_write(0x22054,0x0000000a); /* Blitter Idle Max Count */ |
| 470 | |
| 471 | /* 10 */ |
| 472 | gtt_write(0xa0b0, 0x00000000); /* Unblock Ack to Busy */ |
| 473 | gtt_write(0xa0b4, 0x000003e8); /* RC1e Threshold */ |
| 474 | gtt_write(0xa0b8, 0x0000c350); /* RC6 Threshold */ |
| 475 | gtt_write(0xa0bc, 0x000186a0); /* RC6p Threshold */ |
| 476 | gtt_write(0xa0c0, 0x0000fa00); /* RC6pp Threshold */ |
| 477 | |
| 478 | /* 11 */ |
| 479 | gtt_write(0xa010, 0x000f4240); /* RP Down Timeout */ |
| 480 | gtt_write(0xa014, 0x12060000); /* RP Interrupt Limits */ |
| 481 | gtt_write(0xa02c, 0x00015f90); /* RP Up Threshold */ |
| 482 | gtt_write(0xa030, 0x000186a0); /* RP Down Threshold */ |
| 483 | gtt_write(0xa068, 0x000186a0); /* RP Up EI */ |
| 484 | gtt_write(0xa06c, 0x000493e0); /* RP Down EI */ |
| 485 | gtt_write(0xa070, 0x0000000a); /* RP Idle Hysteresis */ |
| 486 | |
| 487 | /* 11a: Enable Render Standby (RC6) */ |
| 488 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { |
Duncan Laurie | da83a5f | 2012-05-25 10:04:17 -0700 | [diff] [blame] | 489 | /* |
| 490 | * IvyBridge should also support DeepRenderStandby. |
| 491 | * |
| 492 | * Unfortunately it does not work reliably on all SKUs so |
| 493 | * disable it here and it can be enabled by the kernel. |
| 494 | */ |
| 495 | gtt_write(0xa090, 0x88040000); /* HW RC Control */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 496 | } else { |
| 497 | gtt_write(0xa090, 0x88040000); /* HW RC Control */ |
| 498 | } |
| 499 | |
| 500 | /* 12: Normal Frequency Request */ |
| 501 | /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 (8 bits!? use 7) */ |
| 502 | reg32 = MCHBAR32(0x5998); |
| 503 | reg32 >>= 16; |
| 504 | reg32 &= 0xef; |
| 505 | reg32 <<= 25; |
| 506 | gtt_write(0xa008, reg32); |
| 507 | |
| 508 | /* 13: RP Control */ |
| 509 | gtt_write(0xa024, 0x00000592); |
| 510 | |
| 511 | /* 14: Enable PM Interrupts */ |
| 512 | gtt_write(0x4402c, 0x03000076); |
| 513 | |
| 514 | /* Clear 0x6c024 [8:6] */ |
| 515 | reg32 = gtt_read(0x6c024); |
| 516 | reg32 &= ~0x000001c0; |
| 517 | gtt_write(0x6c024, reg32); |
Nico Huber | 07e206a | 2016-10-19 15:20:17 +0200 | [diff] [blame] | 518 | |
| 519 | /* Initialize DP buffer translation with recommended defaults */ |
| 520 | gtt_write(0xe4f00, 0x0100030c); |
| 521 | gtt_write(0xe4f04, 0x00b8230c); |
| 522 | gtt_write(0xe4f08, 0x06f8930c); |
| 523 | gtt_write(0xe4f0c, 0x05f8e38e); |
| 524 | gtt_write(0xe4f10, 0x00b8030c); |
| 525 | gtt_write(0xe4f14, 0x0b78830c); |
| 526 | gtt_write(0xe4f18, 0x09f8d3cf); |
| 527 | gtt_write(0xe4f1c, 0x01e8030c); |
| 528 | gtt_write(0xe4f20, 0x09f863cf); |
| 529 | gtt_write(0xe4f24, 0x0ff803cf); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 530 | } |
| 531 | |
| 532 | static void gma_pm_init_post_vbios(struct device *dev) |
| 533 | { |
| 534 | struct northbridge_intel_sandybridge_config *conf = dev->chip_info; |
| 535 | u32 reg32; |
| 536 | |
| 537 | printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n"); |
| 538 | |
| 539 | /* 15: Deassert Force Wake */ |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 540 | if (bridge_silicon_revision() < IVB_STEP_C0) { |
| 541 | gtt_write(0xa18c, gtt_read(0xa18c) & ~1); |
Duncan Laurie | da83a5f | 2012-05-25 10:04:17 -0700 | [diff] [blame] | 542 | gtt_poll(0x130090, (1 << 0), (0 << 0)); |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 543 | } else { |
| 544 | gtt_write(0xa188, 0x1fffe); |
Duncan Laurie | da83a5f | 2012-05-25 10:04:17 -0700 | [diff] [blame] | 545 | if (gtt_poll(0x130040, (1 << 0), (0 << 0))) |
| 546 | gtt_write(0xa188, gtt_read(0xa188) | 1); |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 547 | } |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 548 | |
| 549 | /* 16: SW RC Control */ |
| 550 | gtt_write(0xa094, 0x00060000); |
| 551 | |
| 552 | /* Setup Digital Port Hotplug */ |
| 553 | reg32 = gtt_read(0xc4030); |
| 554 | if (!reg32) { |
| 555 | reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2; |
| 556 | reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10; |
| 557 | reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18; |
| 558 | gtt_write(0xc4030, reg32); |
| 559 | } |
| 560 | |
| 561 | /* Setup Panel Power On Delays */ |
| 562 | reg32 = gtt_read(0xc7208); |
| 563 | if (!reg32) { |
| 564 | reg32 = (conf->gpu_panel_port_select & 0x3) << 30; |
| 565 | reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16; |
| 566 | reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); |
| 567 | gtt_write(0xc7208, reg32); |
| 568 | } |
| 569 | |
| 570 | /* Setup Panel Power Off Delays */ |
| 571 | reg32 = gtt_read(0xc720c); |
| 572 | if (!reg32) { |
| 573 | reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; |
| 574 | reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); |
| 575 | gtt_write(0xc720c, reg32); |
| 576 | } |
| 577 | |
| 578 | /* Setup Panel Power Cycle Delay */ |
| 579 | if (conf->gpu_panel_power_cycle_delay) { |
| 580 | reg32 = gtt_read(0xc7210); |
| 581 | reg32 &= ~0xff; |
| 582 | reg32 |= conf->gpu_panel_power_cycle_delay & 0xff; |
| 583 | gtt_write(0xc7210, reg32); |
| 584 | } |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 585 | |
| 586 | /* Enable Backlight if needed */ |
| 587 | if (conf->gpu_cpu_backlight) { |
| 588 | gtt_write(0x48250, (1 << 31)); |
| 589 | gtt_write(0x48254, conf->gpu_cpu_backlight); |
| 590 | } |
| 591 | if (conf->gpu_pch_backlight) { |
| 592 | gtt_write(0xc8250, (1 << 31)); |
| 593 | gtt_write(0xc8254, conf->gpu_pch_backlight); |
| 594 | } |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 595 | } |
| 596 | |
Patrick Rudolph | 76b93fe | 2017-06-20 17:55:40 +0200 | [diff] [blame] | 597 | /* Enable SCI to ACPI _GPE._L06 */ |
| 598 | static void gma_enable_swsci(void) |
| 599 | { |
| 600 | u16 reg16; |
| 601 | |
| 602 | /* clear DMISCI status */ |
| 603 | reg16 = inw(DEFAULT_PMBASE + TCO1_STS); |
| 604 | reg16 &= DMISCI_STS; |
| 605 | outw(DEFAULT_PMBASE + TCO1_STS, reg16); |
| 606 | |
| 607 | /* clear acpi tco status */ |
| 608 | outl(DEFAULT_PMBASE + GPE0_STS, TCOSCI_STS); |
| 609 | |
| 610 | /* enable acpi tco scis */ |
| 611 | reg16 = inw(DEFAULT_PMBASE + GPE0_EN); |
| 612 | reg16 |= TCOSCI_EN; |
| 613 | outw(DEFAULT_PMBASE + GPE0_EN, reg16); |
| 614 | } |
| 615 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 616 | static void gma_func0_init(struct device *dev) |
| 617 | { |
| 618 | u32 reg32; |
| 619 | |
| 620 | /* IGD needs to be Bus Master */ |
| 621 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 622 | reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; |
| 623 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 624 | |
| 625 | /* Init graphics power management */ |
| 626 | gma_pm_init_pre_vbios(dev); |
| 627 | |
Alexandru Gagniuc | 9647094 | 2015-09-07 03:06:31 -0700 | [diff] [blame] | 628 | if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) |
| 629 | /* PCI Init, will run VBIOS */ |
| 630 | pci_dev_init(dev); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 631 | |
| 632 | /* Post VBIOS init */ |
| 633 | gma_pm_init_post_vbios(dev); |
Ronald G. Minnich | 69efaa0 | 2013-02-26 10:07:40 -0800 | [diff] [blame] | 634 | |
Patrick Rudolph | de4a1a0 | 2017-06-20 19:13:33 +0200 | [diff] [blame] | 635 | /* Running graphics init on S3 breaks Linux drm driver. */ |
| 636 | if (!acpi_is_wakeup_s3() && |
| 637 | (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) || |
| 638 | IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT))) { |
Alexandru Gagniuc | 9647094 | 2015-09-07 03:06:31 -0700 | [diff] [blame] | 639 | /* This should probably run before post VBIOS init. */ |
| 640 | printk(BIOS_SPEW, "Initializing VGA without OPROM.\n"); |
| 641 | u8 *mmiobase; |
| 642 | u32 iobase, physbase, graphics_base; |
| 643 | struct northbridge_intel_sandybridge_config *conf = dev->chip_info; |
| 644 | iobase = dev->resource_list[2].base; |
| 645 | mmiobase = res2mmio(&dev->resource_list[0], 0, 0); |
| 646 | physbase = pci_read_config32(dev, 0x5c) & ~0xf; |
| 647 | graphics_base = dev->resource_list[1].base; |
Ronald G. Minnich | 69efaa0 | 2013-02-26 10:07:40 -0800 | [diff] [blame] | 648 | |
Nico Huber | 88c6487 | 2016-10-05 18:02:01 +0200 | [diff] [blame] | 649 | int lightup_ok; |
| 650 | if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { |
| 651 | gma_gfxinit((uintptr_t)mmiobase, graphics_base, |
| 652 | physbase, &lightup_ok); |
| 653 | } else { |
| 654 | lightup_ok = i915lightup_sandy(&conf->gfx, physbase, |
| 655 | iobase, mmiobase, graphics_base); |
| 656 | } |
Alexandru Gagniuc | 9647094 | 2015-09-07 03:06:31 -0700 | [diff] [blame] | 657 | if (lightup_ok) |
| 658 | gfx_set_init_done(1); |
| 659 | } |
Patrick Rudolph | 76b93fe | 2017-06-20 17:55:40 +0200 | [diff] [blame] | 660 | |
| 661 | gma_enable_swsci(); |
| 662 | intel_gma_restore_opregion(); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 663 | } |
| 664 | |
| 665 | static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 666 | { |
| 667 | if (!vendor || !device) { |
| 668 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 669 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 670 | } else { |
| 671 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 672 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 673 | } |
| 674 | } |
| 675 | |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 676 | const struct i915_gpu_controller_info * |
| 677 | intel_gma_get_controller_info(void) |
| 678 | { |
| 679 | device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); |
| 680 | if (!dev) { |
| 681 | return NULL; |
| 682 | } |
| 683 | struct northbridge_intel_sandybridge_config *chip = dev->chip_info; |
| 684 | return &chip->gfx; |
| 685 | } |
| 686 | |
Alexander Couzens | 5eea458 | 2015-04-12 22:18:55 +0200 | [diff] [blame] | 687 | static void gma_ssdt(device_t device) |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 688 | { |
| 689 | const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); |
| 690 | if (!gfx) { |
| 691 | return; |
| 692 | } |
| 693 | |
| 694 | drivers_intel_gma_displays_ssdt_generate(gfx); |
| 695 | } |
| 696 | |
Patrick Rudolph | 281ccca | 2017-04-12 16:55:32 +0200 | [diff] [blame] | 697 | static unsigned long |
| 698 | gma_write_acpi_tables(struct device *const dev, |
| 699 | unsigned long current, |
| 700 | struct acpi_rsdp *const rsdp) |
| 701 | { |
Patrick Rudolph | 402e9c1 | 2017-05-18 18:26:30 +0200 | [diff] [blame] | 702 | igd_opregion_t *opregion = (igd_opregion_t *)current; |
Patrick Rudolph | 281ccca | 2017-04-12 16:55:32 +0200 | [diff] [blame] | 703 | global_nvs_t *gnvs; |
| 704 | |
Matt DeVillier | ebe08e0 | 2017-07-14 13:28:42 -0500 | [diff] [blame] | 705 | if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) |
Patrick Rudolph | 402e9c1 | 2017-05-18 18:26:30 +0200 | [diff] [blame] | 706 | return current; |
| 707 | |
| 708 | current += sizeof(igd_opregion_t); |
| 709 | |
| 710 | /* GNVS has been already set up */ |
| 711 | gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 712 | if (gnvs) { |
| 713 | /* IGD OpRegion Base Address */ |
Patrick Rudolph | 19c2ad8 | 2017-06-30 14:52:01 +0200 | [diff] [blame] | 714 | gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); |
Patrick Rudolph | 402e9c1 | 2017-05-18 18:26:30 +0200 | [diff] [blame] | 715 | } else { |
| 716 | printk(BIOS_ERR, "Error: GNVS table not found.\n"); |
Patrick Rudolph | 281ccca | 2017-04-12 16:55:32 +0200 | [diff] [blame] | 717 | } |
| 718 | |
Patrick Rudolph | 402e9c1 | 2017-05-18 18:26:30 +0200 | [diff] [blame] | 719 | current = acpi_align_current(current); |
Patrick Rudolph | 281ccca | 2017-04-12 16:55:32 +0200 | [diff] [blame] | 720 | return current; |
| 721 | } |
| 722 | |
Aaron Durbin | aa090cb | 2017-09-13 16:01:52 -0600 | [diff] [blame] | 723 | static const char *gma_acpi_name(const struct device *dev) |
Patrick Rudolph | 3e47fc9 | 2017-06-07 09:44:07 +0200 | [diff] [blame] | 724 | { |
| 725 | return "GFX0"; |
| 726 | } |
| 727 | |
Patrick Rudolph | e11f6c3 | 2015-10-15 15:35:12 +0200 | [diff] [blame] | 728 | /* called by pci set_vga_bridge function */ |
| 729 | static void gma_func0_disable(struct device *dev) |
| 730 | { |
| 731 | u16 reg16; |
| 732 | device_t dev_host = dev_find_slot(0, PCI_DEVFN(0,0)); |
| 733 | |
| 734 | reg16 = pci_read_config16(dev_host, GGC); |
| 735 | reg16 |= (1 << 1); /* disable VGA decode */ |
| 736 | pci_write_config16(dev_host, GGC, reg16); |
| 737 | |
| 738 | dev->enabled = 0; |
| 739 | } |
| 740 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 741 | static struct pci_operations gma_pci_ops = { |
| 742 | .set_subsystem = gma_set_subsystem, |
| 743 | }; |
| 744 | |
| 745 | static struct device_operations gma_func0_ops = { |
Vladimir Serbinenko | 30fe612 | 2014-02-05 23:25:28 +0100 | [diff] [blame] | 746 | .read_resources = pci_dev_read_resources, |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 747 | .set_resources = pci_dev_set_resources, |
| 748 | .enable_resources = pci_dev_enable_resources, |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 749 | .acpi_fill_ssdt_generator = gma_ssdt, |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 750 | .init = gma_func0_init, |
| 751 | .scan_bus = 0, |
| 752 | .enable = 0, |
Patrick Rudolph | e11f6c3 | 2015-10-15 15:35:12 +0200 | [diff] [blame] | 753 | .disable = gma_func0_disable, |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 754 | .ops_pci = &gma_pci_ops, |
Patrick Rudolph | 3e47fc9 | 2017-06-07 09:44:07 +0200 | [diff] [blame] | 755 | .acpi_name = gma_acpi_name, |
Patrick Rudolph | 281ccca | 2017-04-12 16:55:32 +0200 | [diff] [blame] | 756 | .write_acpi_tables = gma_write_acpi_tables, |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 757 | }; |
| 758 | |
Ronald G. Minnich | 69efaa0 | 2013-02-26 10:07:40 -0800 | [diff] [blame] | 759 | static const unsigned short pci_device_ids[] = { 0x0102, 0x0106, 0x010a, 0x0112, |
| 760 | 0x0116, 0x0122, 0x0126, 0x0156, |
Vagiz Trakhanov | 1dd448c | 2017-09-28 14:42:11 +0000 | [diff] [blame] | 761 | 0x0166, 0x0162, 0x016a, 0x0152, |
Ronald G. Minnich | 69efaa0 | 2013-02-26 10:07:40 -0800 | [diff] [blame] | 762 | 0 }; |
| 763 | |
| 764 | static const struct pci_driver gma __pci_driver = { |
| 765 | .ops = &gma_func0_ops, |
| 766 | .vendor = PCI_VENDOR_ID_INTEL, |
| 767 | .devices = pci_device_ids, |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 768 | }; |