Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <acpi/acpi.h> |
| 4 | #include <acpi/acpi_gnvs.h> |
| 5 | #include <acpi/acpigen.h> |
| 6 | #include <device/mmio.h> |
| 7 | #include <arch/smp/mpspec.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 8 | #include <console/console.h> |
| 9 | #include <device/device.h> |
| 10 | #include <device/pci_ops.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 11 | #include <intelblocks/cpulib.h> |
| 12 | #include <intelblocks/pmclib.h> |
| 13 | #include <intelblocks/acpi.h> |
| 14 | #include <soc/cpu.h> |
| 15 | #include <soc/iomap.h> |
| 16 | #include <soc/nvs.h> |
| 17 | #include <soc/pci_devs.h> |
| 18 | #include <soc/pm.h> |
| 19 | #include <soc/soc_chip.h> |
| 20 | #include <soc/systemagent.h> |
| 21 | #include <string.h> |
| 22 | #include <types.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 23 | |
| 24 | /* |
| 25 | * List of supported C-states in this processor. |
| 26 | */ |
| 27 | enum { |
| 28 | C_STATE_C0, /* 0 */ |
| 29 | C_STATE_C1, /* 1 */ |
| 30 | C_STATE_C1E, /* 2 */ |
| 31 | C_STATE_C6_SHORT_LAT, /* 3 */ |
| 32 | C_STATE_C6_LONG_LAT, /* 4 */ |
| 33 | C_STATE_C7_SHORT_LAT, /* 5 */ |
| 34 | C_STATE_C7_LONG_LAT, /* 6 */ |
| 35 | C_STATE_C7S_SHORT_LAT, /* 7 */ |
| 36 | C_STATE_C7S_LONG_LAT, /* 8 */ |
| 37 | C_STATE_C8, /* 9 */ |
| 38 | C_STATE_C9, /* 10 */ |
| 39 | C_STATE_C10, /* 11 */ |
| 40 | NUM_C_STATES |
| 41 | }; |
| 42 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 43 | static const acpi_cstate_t cstate_map[NUM_C_STATES] = { |
| 44 | [C_STATE_C0] = {}, |
| 45 | [C_STATE_C1] = { |
| 46 | .latency = C1_LATENCY, |
| 47 | .power = C1_POWER, |
| 48 | .resource = MWAIT_RES(0, 0), |
| 49 | }, |
| 50 | [C_STATE_C1E] = { |
| 51 | .latency = C1_LATENCY, |
| 52 | .power = C1_POWER, |
| 53 | .resource = MWAIT_RES(0, 1), |
| 54 | }, |
| 55 | [C_STATE_C6_SHORT_LAT] = { |
| 56 | .latency = C6_LATENCY, |
| 57 | .power = C6_POWER, |
| 58 | .resource = MWAIT_RES(2, 0), |
| 59 | }, |
| 60 | [C_STATE_C6_LONG_LAT] = { |
| 61 | .latency = C6_LATENCY, |
| 62 | .power = C6_POWER, |
| 63 | .resource = MWAIT_RES(2, 1), |
| 64 | }, |
| 65 | [C_STATE_C7_SHORT_LAT] = { |
| 66 | .latency = C7_LATENCY, |
| 67 | .power = C7_POWER, |
| 68 | .resource = MWAIT_RES(3, 0), |
| 69 | }, |
| 70 | [C_STATE_C7_LONG_LAT] = { |
| 71 | .latency = C7_LATENCY, |
| 72 | .power = C7_POWER, |
| 73 | .resource = MWAIT_RES(3, 1), |
| 74 | }, |
| 75 | [C_STATE_C7S_SHORT_LAT] = { |
| 76 | .latency = C7_LATENCY, |
| 77 | .power = C7_POWER, |
| 78 | .resource = MWAIT_RES(3, 2), |
| 79 | }, |
| 80 | [C_STATE_C7S_LONG_LAT] = { |
| 81 | .latency = C7_LATENCY, |
| 82 | .power = C7_POWER, |
| 83 | .resource = MWAIT_RES(3, 3), |
| 84 | }, |
| 85 | [C_STATE_C8] = { |
| 86 | .latency = C8_LATENCY, |
| 87 | .power = C8_POWER, |
| 88 | .resource = MWAIT_RES(4, 0), |
| 89 | }, |
| 90 | [C_STATE_C9] = { |
| 91 | .latency = C9_LATENCY, |
| 92 | .power = C9_POWER, |
| 93 | .resource = MWAIT_RES(5, 0), |
| 94 | }, |
| 95 | [C_STATE_C10] = { |
| 96 | .latency = C10_LATENCY, |
| 97 | .power = C10_POWER, |
| 98 | .resource = MWAIT_RES(6, 0), |
| 99 | }, |
| 100 | }; |
| 101 | |
| 102 | static int cstate_set_non_s0ix[] = { |
| 103 | C_STATE_C1, |
| 104 | C_STATE_C6_LONG_LAT, |
| 105 | C_STATE_C7S_LONG_LAT |
| 106 | }; |
| 107 | |
| 108 | static int cstate_set_s0ix[] = { |
| 109 | C_STATE_C1, |
| 110 | C_STATE_C7S_LONG_LAT, |
| 111 | C_STATE_C10 |
| 112 | }; |
| 113 | |
| 114 | acpi_cstate_t *soc_get_cstate_map(size_t *entries) |
| 115 | { |
| 116 | static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix), |
| 117 | ARRAY_SIZE(cstate_set_non_s0ix))]; |
| 118 | int *set; |
| 119 | int i; |
| 120 | |
| 121 | config_t *config = config_of_soc(); |
| 122 | |
| 123 | int is_s0ix_enable = config->s0ix_enable; |
| 124 | |
| 125 | if (is_s0ix_enable) { |
| 126 | *entries = ARRAY_SIZE(cstate_set_s0ix); |
| 127 | set = cstate_set_s0ix; |
| 128 | } else { |
| 129 | *entries = ARRAY_SIZE(cstate_set_non_s0ix); |
| 130 | set = cstate_set_non_s0ix; |
| 131 | } |
| 132 | |
| 133 | for (i = 0; i < *entries; i++) { |
| 134 | memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t)); |
| 135 | map[i].ctype = i + 1; |
| 136 | } |
| 137 | return map; |
| 138 | } |
| 139 | |
| 140 | void soc_power_states_generation(int core_id, int cores_per_package) |
| 141 | { |
| 142 | config_t *config = config_of_soc(); |
| 143 | |
| 144 | if (config->eist_enable) |
| 145 | /* Generate P-state tables */ |
| 146 | generate_p_state_entries(core_id, cores_per_package); |
| 147 | } |
| 148 | |
| 149 | void soc_fill_fadt(acpi_fadt_t *fadt) |
| 150 | { |
| 151 | const uint16_t pmbase = ACPI_BASE_ADDRESS; |
| 152 | |
| 153 | config_t *config = config_of_soc(); |
| 154 | |
| 155 | fadt->pm_tmr_blk = pmbase + PM1_TMR; |
| 156 | fadt->pm_tmr_len = 4; |
| 157 | fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 158 | fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; |
| 159 | fadt->x_pm_tmr_blk.bit_offset = 0; |
| 160 | fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; |
| 161 | fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; |
| 162 | fadt->x_pm_tmr_blk.addrh = 0x0; |
| 163 | |
| 164 | if (config->s0ix_enable) |
| 165 | fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; |
| 166 | } |
| 167 | |
| 168 | uint32_t soc_read_sci_irq_select(void) |
| 169 | { |
| 170 | return read32((void *)soc_read_pmc_base() + IRQ_REG); |
| 171 | } |
| 172 | |
| 173 | static unsigned long soc_fill_dmar(unsigned long current) |
| 174 | { |
| 175 | const struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); |
| 176 | const uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK; |
| 177 | const bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED; |
| 178 | |
| 179 | if (is_dev_enabled(igfx_dev) && gfxvtbar && gfxvten) { |
| 180 | const unsigned long tmp = current; |
| 181 | |
| 182 | current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); |
John Zhao | baecee1 | 2021-04-23 10:29:12 -0700 | [diff] [blame] | 183 | current += acpi_create_dmar_ds_pci(current, 0, SA_DEV_SLOT_IGD, 0); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 184 | |
| 185 | acpi_dmar_drhd_fixup(tmp, current); |
| 186 | } |
| 187 | |
| 188 | const struct device *const ipu_dev = pcidev_path_on_root(SA_DEVFN_IPU); |
| 189 | const uint64_t ipuvtbar = MCHBAR64(IPUVTBAR) & VTBAR_MASK; |
| 190 | const bool ipuvten = MCHBAR32(IPUVTBAR) & VTBAR_ENABLED; |
| 191 | |
| 192 | if (is_dev_enabled(ipu_dev) && ipuvtbar && ipuvten) { |
| 193 | const unsigned long tmp = current; |
| 194 | |
| 195 | current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar); |
John Zhao | baecee1 | 2021-04-23 10:29:12 -0700 | [diff] [blame] | 196 | current += acpi_create_dmar_ds_pci(current, 0, SA_DEV_SLOT_IPU, 0); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 197 | |
| 198 | acpi_dmar_drhd_fixup(tmp, current); |
| 199 | } |
| 200 | |
John Zhao | 24ae31c | 2021-04-17 13:45:00 -0700 | [diff] [blame] | 201 | /* TCSS Thunderbolt root ports */ |
| 202 | for (unsigned int i = 0; i < MAX_TBT_PCIE_PORT; i++) { |
| 203 | const struct device *const tbt_dev = pcidev_path_on_root(SA_DEVFN_TBT(i)); |
| 204 | if (is_dev_enabled(tbt_dev)) { |
| 205 | const uint64_t tbtbar = MCHBAR64(TBTxBAR(i)) & VTBAR_MASK; |
| 206 | const bool tbten = MCHBAR32(TBTxBAR(i)) & VTBAR_ENABLED; |
| 207 | if (tbtbar && tbten) { |
| 208 | const unsigned long tmp = current; |
| 209 | |
| 210 | current += acpi_create_dmar_drhd(current, 0, 0, tbtbar); |
John Zhao | baecee1 | 2021-04-23 10:29:12 -0700 | [diff] [blame] | 211 | current += acpi_create_dmar_ds_pci_br(current, 0, |
| 212 | SA_DEV_SLOT_TBT, i); |
John Zhao | 24ae31c | 2021-04-17 13:45:00 -0700 | [diff] [blame] | 213 | |
| 214 | acpi_dmar_drhd_fixup(tmp, current); |
| 215 | } |
| 216 | } |
| 217 | } |
| 218 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 219 | const uint64_t vtvc0bar = MCHBAR64(VTVC0BAR) & VTBAR_MASK; |
| 220 | const bool vtvc0en = MCHBAR32(VTVC0BAR) & VTBAR_ENABLED; |
| 221 | |
| 222 | if (vtvc0bar && vtvc0en) { |
| 223 | const unsigned long tmp = current; |
| 224 | |
| 225 | current += acpi_create_dmar_drhd(current, |
| 226 | DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); |
| 227 | current += acpi_create_dmar_ds_ioapic(current, |
| 228 | 2, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, |
| 229 | V_P2SB_CFG_IBDF_FUNC); |
| 230 | current += acpi_create_dmar_ds_msi_hpet(current, |
| 231 | 0, V_P2SB_CFG_HBDF_BUS, V_P2SB_CFG_HBDF_DEV, |
| 232 | V_P2SB_CFG_HBDF_FUNC); |
| 233 | |
| 234 | acpi_dmar_drhd_fixup(tmp, current); |
| 235 | } |
| 236 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 237 | /* Add RMRR entry */ |
| 238 | if (is_dev_enabled(igfx_dev)) { |
| 239 | const unsigned long tmp = current; |
| 240 | current += acpi_create_dmar_rmrr(current, 0, |
| 241 | sa_get_gsm_base(), sa_get_tolud_base() - 1); |
John Zhao | baecee1 | 2021-04-23 10:29:12 -0700 | [diff] [blame] | 242 | current += acpi_create_dmar_ds_pci(current, 0, SA_DEV_SLOT_IGD, 0); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 243 | acpi_dmar_rmrr_fixup(tmp, current); |
| 244 | } |
| 245 | |
| 246 | return current; |
| 247 | } |
| 248 | |
| 249 | unsigned long sa_write_acpi_tables(const struct device *dev, unsigned long current, |
| 250 | struct acpi_rsdp *rsdp) |
| 251 | { |
| 252 | acpi_dmar_t *const dmar = (acpi_dmar_t *)current; |
| 253 | |
| 254 | /* |
| 255 | * Create DMAR table only if we have VT-d capability and FSP does not override its |
| 256 | * feature. |
| 257 | */ |
| 258 | if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) || |
| 259 | !(MCHBAR32(VTVC0BAR) & VTBAR_ENABLED)) |
| 260 | return current; |
| 261 | |
| 262 | printk(BIOS_DEBUG, "ACPI: * DMAR\n"); |
| 263 | acpi_create_dmar(dmar, DMAR_INTR_REMAP | DMA_CTRL_PLATFORM_OPT_IN_FLAG, soc_fill_dmar); |
| 264 | current += dmar->header.length; |
| 265 | current = acpi_align_current(current); |
| 266 | acpi_add_table(rsdp, dmar); |
| 267 | |
| 268 | return current; |
| 269 | } |
| 270 | |
Kyösti Mälkki | c2b0a4f | 2020-06-28 22:39:59 +0300 | [diff] [blame] | 271 | void soc_fill_gnvs(struct global_nvs *gnvs) |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 272 | { |
| 273 | config_t *config = config_of_soc(); |
| 274 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 275 | /* Enable DPTF based on mainboard configuration */ |
| 276 | gnvs->dpte = config->dptf_enable; |
| 277 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 278 | /* Set USB2/USB3 wake enable bitmaps. */ |
| 279 | gnvs->u2we = config->usb2_wake_enable_bitmap; |
| 280 | gnvs->u3we = config->usb3_wake_enable_bitmap; |
| 281 | |
| 282 | /* Fill in Above 4GB MMIO resource */ |
| 283 | sa_fill_gnvs(gnvs); |
| 284 | } |
| 285 | |
| 286 | uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, |
| 287 | const struct chipset_power_state *ps) |
| 288 | { |
| 289 | /* |
| 290 | * WAK_STS bit is set when the system is in one of the sleep states |
| 291 | * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting |
| 292 | * this bit, the PMC will transition the system to the ON state and |
| 293 | * can only be set by hardware and can only be cleared by writing a one |
| 294 | * to this bit position. |
| 295 | */ |
| 296 | |
| 297 | generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; |
| 298 | return generic_pm1_en; |
| 299 | } |
| 300 | |
| 301 | int soc_madt_sci_irq_polarity(int sci) |
| 302 | { |
| 303 | return MP_IRQ_POLARITY_HIGH; |
| 304 | } |