Arthur Heymans | 306521b | 2016-10-27 00:34:18 +0200 | [diff] [blame] | 1 | subdirs-y += ../model_6fx |
| 2 | subdirs-y += ../model_1067x |
| 3 | subdirs-y += ../../x86/tsc |
| 4 | subdirs-y += ../../x86/mtrr |
| 5 | subdirs-y += ../../x86/lapic |
| 6 | subdirs-y += ../../x86/cache |
| 7 | subdirs-y += ../../x86/smm |
| 8 | subdirs-y += ../microcode |
| 9 | subdirs-y += ../hyperthreading |
| 10 | subdirs-y += ../speedstep |
| 11 | |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 12 | ifneq ($(CONFIG_POSTCAR_STAGE),y) |
Arthur Heymans | 306521b | 2016-10-27 00:34:18 +0200 | [diff] [blame] | 13 | cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc |
Arthur Heymans | 7a8205b | 2018-06-03 10:29:07 +0200 | [diff] [blame] | 14 | else |
| 15 | cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S |
| 16 | postcar-y += ../car/p4-netburst/exit_car.S |
| 17 | endif |
| 18 | |
Arthur Heymans | 306521b | 2016-10-27 00:34:18 +0200 | [diff] [blame] | 19 | romstage-y += ../car/romstage.c |