blob: ef89ac65a1b6bb3fa0366692071722e08768a38a [file] [log] [blame]
Arthur Heymans306521b2016-10-27 00:34:18 +02001subdirs-y += ../model_6fx
2subdirs-y += ../model_1067x
3subdirs-y += ../../x86/tsc
4subdirs-y += ../../x86/mtrr
5subdirs-y += ../../x86/lapic
6subdirs-y += ../../x86/cache
7subdirs-y += ../../x86/smm
8subdirs-y += ../microcode
9subdirs-y += ../hyperthreading
10subdirs-y += ../speedstep
11
Arthur Heymans7a8205b2018-06-03 10:29:07 +020012ifneq ($(CONFIG_POSTCAR_STAGE),y)
Arthur Heymans306521b2016-10-27 00:34:18 +020013cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
Arthur Heymans7a8205b2018-06-03 10:29:07 +020014else
15cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S
16postcar-y += ../car/p4-netburst/exit_car.S
17endif
18
Arthur Heymans306521b2016-10-27 00:34:18 +020019romstage-y += ../car/romstage.c