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review.coreboot.org / coreboot / 4f8ff240dd45fc568b05bb17bea5afca7a8ce75c / . / src / southbridge / rdc / r8610 / r8610.c
blob: f53ce6612dbd2942414a7b4ea615d9e7ded43e49 [file] [log] [blame]
Rudolf Marek6b89b4c2012-03-25 18:16:11 +0200[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Rudolf Marek <r.marek@assembler.cz>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Rudolf Marek6b89b4c2012-03-25 18:16:11 +0200[diff] [blame]14 */
15
16#include <arch/io.h>
17#include <console/console.h>
18#include <device/device.h>
19#include <device/pci.h>
20#include <device/pci_ids.h>
21#include <pc80/i8259.h>
22#include <stdlib.h>
23
24static const unsigned char enetIrqs[4] = { 10, 0, 0, 0 };
25static const unsigned char usbIrqs[4] = { 15, 14, 0, 0 };
26
27static void pci_routing_fixup(struct device *dev)
28{
29 pci_assign_irqs(0, 0x8, enetIrqs);
30 pci_assign_irqs(0, 0xa, usbIrqs);
31}
32
33static void r8610_init(struct device *dev)
34{
35 device_t nb_dev;
36 u32 tmp;
37
38 printk(BIOS_DEBUG, "r8610 init\n");
39
40 /* clear DMA? */
41 outb(0x4, 0x8);
42 outb(0x4, 0x10);
43
44 outb(0xfc, 0x61);
45
46 /* Set serial base */
47 pci_write_config32(dev, 0x54, 0x3f8);
48 /* serial IRQ disable, LPC disable, COM2 goes to LPC, internal UART for COM1 */
49 pci_write_config32(dev, 0x50, 0x84101012);
50
51 /* Enable internal Port92, enable chipselect for flash */
52 tmp = pci_read_config32(dev, 0x40);
53 pci_write_config32(dev, 0x40, tmp | 0x07FF0600);
54
55 /* buffer strength SB pins */
56 pci_write_config32(dev, 0x5c, 0x2315);
57
58 /* EHCI 14, OHCI 15, MAC1 disable, MAC0 10, INTD 9, INTC 9, INTB 12, INTA INT10 */
59 pci_write_config32(dev, 0x58, 0xdf0311b3);
60
61 /* USB PHY control */
62 nb_dev = dev_find_device(PCI_VENDOR_ID_RDC,
63 PCI_DEVICE_ID_RDC_R8610_NB, 0);
64
65 tmp = pci_read_config32(nb_dev, 0xc0);
66 tmp |= 0x40000;
67 pci_write_config32(nb_dev, 0xc0, tmp);
68
69 setup_i8259();
70}
71
72static void r8610_read_resources(device_t dev)
73{
74 struct resource *res;
75
76 pci_dev_read_resources(dev);
77
78 res = new_resource(dev, 1);
79 res->base = 0x0UL;
80 res->size = 0x1000UL;
81 res->limit = 0xffffUL;
82 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
83
84 /* Reserve space for flash */
85 res = new_resource(dev, 2);
86 res->base = 0xff800000;
87 res->size = 8*1024*1024;
88 res->limit = 0xffffffffUL;
89 res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
90 IORESOURCE_ASSIGNED;
91}
92
93static void southbridge_init(struct device *dev)
94{
95 r8610_init(dev);
96 pci_routing_fixup(dev);
97}
98
99static struct device_operations r8610_sb_ops = {
100 .read_resources = r8610_read_resources,
101 .set_resources = pci_dev_set_resources,
102 .enable_resources = pci_dev_enable_resources,
103 .init = &southbridge_init,
Rudolf Marek6b89b4c2012-03-25 18:16:11 +0200[diff] [blame]104 .enable = 0,
105 .ops_pci = 0,
106};
107
108static const struct pci_driver lpc_driver __pci_driver = {
109 .ops = &r8610_sb_ops,
110 .vendor = PCI_VENDOR_ID_RDC,
111 .device = PCI_DEVICE_ID_RDC_R8610_SB,
112};