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Vladimir Serbinenko888d5592013-11-13 17:53:38 +01001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com>
5 * Copyright (C) 2009 coresystems GmbH
6 * Copyright (C) 2013 Vladimir Serbinenko
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Vladimir Serbinenko888d5592013-11-13 17:53:38 +010016 */
17
18#include <device/smbus_def.h>
19#include "pch.h"
20
21static void smbus_delay(void)
22{
23 inb(0x80);
24}
25
26static int smbus_wait_until_ready(u16 smbus_base)
27{
28 unsigned loops = SMBUS_TIMEOUT;
29 unsigned char byte;
30 do {
31 smbus_delay();
32 if (--loops == 0)
33 break;
34 byte = inb(smbus_base + SMBHSTSTAT);
35 } while (byte & 1);
36 return loops ? 0 : -1;
37}
38
39static int smbus_wait_until_done(u16 smbus_base)
40{
41 unsigned loops = SMBUS_TIMEOUT;
42 unsigned char byte;
43 do {
44 smbus_delay();
45 if (--loops == 0)
46 break;
47 byte = inb(smbus_base + SMBHSTSTAT);
48 } while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0);
49 return loops ? 0 : -1;
50}
51
52static int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned address)
53{
54 unsigned char global_status_register;
55 unsigned char byte;
56
57 if (smbus_wait_until_ready(smbus_base) < 0) {
58 return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
59 }
60 /* Setup transaction */
61 /* Disable interrupts */
62 outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
63 /* Set the device I'm talking too */
64 outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD);
65 /* Set the command/address... */
66 outb(address & 0xff, smbus_base + SMBHSTCMD);
67 /* Set up for a byte data read */
68 outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2),
69 (smbus_base + SMBHSTCTL));
70 /* Clear any lingering errors, so the transaction will run */
71 outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
72
73 /* Clear the data byte... */
74 outb(0, smbus_base + SMBHSTDAT0);
75
76 /* Start the command */
77 outb((inb(smbus_base + SMBHSTCTL) | 0x40),
78 smbus_base + SMBHSTCTL);
79
80 /* Poll for transaction completion */
81 if (smbus_wait_until_done(smbus_base) < 0) {
82 return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
83 }
84
85 global_status_register = inb(smbus_base + SMBHSTSTAT);
86
87 /* Ignore the "In Use" status... */
88 global_status_register &= ~(3 << 5);
89
90 /* Read results of transaction */
91 byte = inb(smbus_base + SMBHSTDAT0);
92 if (global_status_register != (1 << 1)) {
93 return SMBUS_ERROR;
94 }
95 return byte;
96}
97
Vladimir Serbinenko888d5592013-11-13 17:53:38 +010098static int do_smbus_write_byte(unsigned smbus_base, unsigned device, unsigned address, unsigned data)
99{
100 unsigned char global_status_register;
101
102 if (smbus_wait_until_ready(smbus_base) < 0)
103 return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
104
105 /* Setup transaction */
106 /* Disable interrupts */
107 outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
108 /* Set the device I'm talking too */
109 outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD);
110 /* Set the command/address... */
111 outb(address & 0xff, smbus_base + SMBHSTCMD);
112 /* Set up for a byte data read */
113 outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2),
114 (smbus_base + SMBHSTCTL));
115 /* Clear any lingering errors, so the transaction will run */
116 outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
117
118 /* Clear the data byte... */
119 outb(data, smbus_base + SMBHSTDAT0);
120
121 /* Start the command */
122 outb((inb(smbus_base + SMBHSTCTL) | 0x40),
123 smbus_base + SMBHSTCTL);
124
125 /* Poll for transaction completion */
126 if (smbus_wait_until_done(smbus_base) < 0)
127 return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
128
129 global_status_register = inb(smbus_base + SMBHSTSTAT);
130
131 /* Ignore the "In Use" status... */
132 global_status_register &= ~(3 << 5);
133
134 /* Read results of transaction */
135 if (global_status_register != (1 << 1))
136 return SMBUS_ERROR;
137
138 return 0;
139}
140
Vladimir Serbinenko5f20dbf2014-01-27 23:57:44 +0100141#ifdef __PRE_RAM__
142
Vladimir Serbinenko888d5592013-11-13 17:53:38 +0100143static int do_smbus_block_write(unsigned smbus_base, unsigned device,
144 unsigned cmd, unsigned bytes, const u8 *buf)
145{
146 u8 status;
147
148 if (smbus_wait_until_ready(smbus_base) < 0)
149 return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
150
151 /* Setup transaction */
152 /* Disable interrupts */
153 outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
154 /* Set the device I'm talking too */
155 outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD);
156 /* Set the command/address... */
157 outb(cmd & 0xff, smbus_base + SMBHSTCMD);
158 /* Set up for a block data write */
159 outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x5 << 2),
160 (smbus_base + SMBHSTCTL));
161 /* Clear any lingering errors, so the transaction will run */
162 outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
163
164 /* set number of bytes to transfer */
165 outb(bytes, smbus_base + SMBHSTDAT0);
166
167 outb(*buf++, smbus_base + SMBBLKDAT);
168 bytes--;
169
170 /* Start the command */
171 outb((inb(smbus_base + SMBHSTCTL) | 0x40),
172 smbus_base + SMBHSTCTL);
173
174 while(!(inb(smbus_base + SMBHSTSTAT) & 1));
175 /* Poll for transaction completion */
176 do {
177 status = inb(smbus_base + SMBHSTSTAT);
178 if (status & ((1 << 4) | /* FAILED */
179 (1 << 3) | /* BUS ERR */
180 (1 << 2))) /* DEV ERR */
181 return SMBUS_ERROR;
182
183 if (status & 0x80) { /* Byte done */
184 outb(*buf++, smbus_base + SMBBLKDAT);
185 outb(status, smbus_base + SMBHSTSTAT);
186 }
187 } while(status & 0x01);
188
189 return 0;
190}
191
192static int do_smbus_block_read(unsigned smbus_base, unsigned device,
193 unsigned cmd, unsigned bytes, u8 *buf)
194{
195 u8 status;
196 int bytes_read = 0;
197 if (smbus_wait_until_ready(smbus_base) < 0)
198 return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
199
200 /* Setup transaction */
201 /* Disable interrupts */
202 outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
203 /* Set the device I'm talking too */
204 outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD);
205 /* Set the command/address... */
206 outb(cmd & 0xff, smbus_base + SMBHSTCMD);
207 /* Set up for a block data read */
208 outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x5 << 2),
209 (smbus_base + SMBHSTCTL));
210 /* Clear any lingering errors, so the transaction will run */
211 outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
212
213 /* Start the command */
214 outb((inb(smbus_base + SMBHSTCTL) | 0x40),
215 smbus_base + SMBHSTCTL);
216
217 while(!(inb(smbus_base + SMBHSTSTAT) & 1));
218 /* Poll for transaction completion */
219 do {
220 status = inb(smbus_base + SMBHSTSTAT);
221 if (status & ((1 << 4) | /* FAILED */
222 (1 << 3) | /* BUS ERR */
223 (1 << 2))) /* DEV ERR */
224 return SMBUS_ERROR;
225
226 if (status & 0x80) { /* Byte done */
227 *buf = inb(smbus_base + SMBBLKDAT);
228 buf++;
229 bytes_read++;
230 outb(status, smbus_base + SMBHSTSTAT);
231 if (--bytes == 1) {
232 /* indicate that next byte is the last one */
233 outb(inb(smbus_base + SMBHSTCTL) | 0x20,
234 smbus_base + SMBHSTCTL);
235 }
236 }
237 } while(status & 0x01);
238
239 return bytes_read;
240}
241#endif