blob: eb25328ffc11bbe5c49fd0bd1ae7bd16dc2b9efa [file] [log] [blame]
Vladimir Serbinenko1cd937b2014-01-09 23:41:48 +01001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2014 Vladimir Serbinenko
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Vladimir Serbinenko1cd937b2014-01-09 23:41:48 +010015 */
16
17#include <arch/io.h>
18#include "pch.h"
Vladimir Serbinenko2bebc802014-02-19 22:02:51 +010019#include "cpu/intel/model_2065x/model_2065x.h"
20#include <cpu/x86/msr.h>
Vladimir Serbinenko1cd937b2014-01-09 23:41:48 +010021
22/* Early thermal init, must be done prior to giving ME its memory
23 which is done at the end of raminit. */
24void early_thermal_init(void)
25{
26 device_t dev;
Vladimir Serbinenko2bebc802014-02-19 22:02:51 +010027 msr_t msr;
Vladimir Serbinenko1cd937b2014-01-09 23:41:48 +010028
29 dev = PCI_DEV(0x0, 0x1f, 0x6);
30
31 /* Program address for temporary BAR. */
32 pci_write_config32(dev, 0x40, 0x40000000);
33 pci_write_config32(dev, 0x44, 0x0);
34
35 /* Activate temporary BAR. */
36 pci_write_config32(dev, 0x40,
37 pci_read_config32(dev, 0x40) | 5);
38
39 /* Perform init. */
Vladimir Serbinenko2bebc802014-02-19 22:02:51 +010040 /* Configure TJmax. */
41 msr = rdmsr(MSR_TEMPERATURE_TARGET);
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080042 write16((u16 *)0x40000012, ((msr.lo >> 16) & 0xff) << 6);
Vladimir Serbinenko2bebc802014-02-19 22:02:51 +010043 /* Northbridge temperature slope and offset. */
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080044 write16((u16 *)0x40000016, 0x7746);
Vladimir Serbinenko2bebc802014-02-19 22:02:51 +010045 /* Enable thermal data reporting, processor, PCH and northbridge. */
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080046 write16((u16 *)0x4000001a,
47 (read16((u16 *)0x4000001a) & ~0xf) | 0x10f0);
Vladimir Serbinenko1cd937b2014-01-09 23:41:48 +010048
49 /* Disable temporary BAR. */
50 pci_write_config32(dev, 0x40,
51 pci_read_config32(dev, 0x40) & ~1);
52 pci_write_config32(dev, 0x40, 0);
53}