Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <arch/io.h> |
| 21 | #include <broadwell/pci_devs.h> |
| 22 | #include <broadwell/systemagent.h> |
| 23 | |
| 24 | static void bootblock_northbridge_init(void) |
| 25 | { |
| 26 | uint32_t reg; |
| 27 | |
| 28 | /* |
| 29 | * The "io" variant of the config access is explicitly used to |
| 30 | * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to |
| 31 | * to true. That way all subsequent non-explicit config accesses use |
| 32 | * MCFG. This code also assumes that bootblock_northbridge_init() is |
| 33 | * the first thing called in the non-asm boot block code. The final |
| 34 | * assumption is that no assembly code is using the |
Martin Roth | de7ed6f | 2014-12-07 14:58:18 -0700 | [diff] [blame] | 35 | * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config accesses. |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 36 | * |
| 37 | * The PCIEXBAR is assumed to live in the memory mapped IO space under |
| 38 | * 4GiB. |
| 39 | */ |
| 40 | reg = 0; |
| 41 | pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg); |
| 42 | reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ |
| 43 | pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg); |
| 44 | } |