Angel Pons | 7544e2f | 2020-04-03 01:23:10 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Dennis Wassenberg | bd10516 | 2015-09-10 12:20:58 +0200 | [diff] [blame] | 2 | |
Arthur Heymans | fa5d0f8 | 2019-11-12 19:11:50 +0100 | [diff] [blame] | 3 | #include <bootblock_common.h> |
Dennis Wassenberg | bd10516 | 2015-09-10 12:20:58 +0200 | [diff] [blame] | 4 | #include <stdint.h> |
Kyösti Mälkki | 3855c01 | 2019-03-03 08:45:19 +0200 | [diff] [blame] | 5 | #include <device/pnp_ops.h> |
Dennis Wassenberg | bd10516 | 2015-09-10 12:20:58 +0200 | [diff] [blame] | 6 | #include <device/pnp.h> |
| 7 | #include <northbridge/intel/sandybridge/raminit.h> |
| 8 | #include <northbridge/intel/sandybridge/raminit_native.h> |
| 9 | #include <northbridge/intel/sandybridge/sandybridge.h> |
| 10 | #include <southbridge/intel/bd82x6x/pch.h> |
| 11 | #include <superio/ite/it8783ef/it8783ef.h> |
| 12 | #include <superio/ite/common/ite.h> |
| 13 | |
Arthur Heymans | fa5d0f8 | 2019-11-12 19:11:50 +0100 | [diff] [blame] | 14 | void bootblock_mainboard_early_init(void) |
Dennis Wassenberg | bd10516 | 2015-09-10 12:20:58 +0200 | [diff] [blame] | 15 | { |
| 16 | const pnp_devfn_t dev = PNP_DEV(0x2e, IT8783EF_GPIO); |
| 17 | |
| 18 | pnp_enter_conf_state(dev); |
| 19 | pnp_set_logical_device(dev); |
| 20 | |
| 21 | pnp_write_config(dev, 0x23, ITE_UART_CLK_PREDIVIDE_24); |
| 22 | |
| 23 | /* Switch multi function for UART4 */ |
| 24 | pnp_write_config(dev, 0x2a, 0x04); |
| 25 | /* Switch multi function for UART3 */ |
| 26 | pnp_write_config(dev, 0x2c, 0x13); |
| 27 | |
| 28 | /* No GPIOs used: Clear any output / pull-up that's set by default */ |
| 29 | pnp_write_config(dev, 0xb8, 0x00); |
| 30 | pnp_write_config(dev, 0xc0, 0x00); |
| 31 | pnp_write_config(dev, 0xc3, 0x00); |
| 32 | pnp_write_config(dev, 0xc8, 0x00); |
| 33 | pnp_write_config(dev, 0xcb, 0x00); |
| 34 | pnp_write_config(dev, 0xef, 0x00); |
| 35 | |
| 36 | pnp_exit_conf_state(dev); |
| 37 | } |
| 38 | |
| 39 | void mainboard_fill_pei_data(struct pei_data *const pei_data) |
| 40 | { |
| 41 | const struct pei_data pei_data_template = { |
| 42 | .pei_version = PEI_VERSION, |
Angel Pons | d9e58dc | 2021-01-20 01:22:20 +0100 | [diff] [blame] | 43 | .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, |
| 44 | .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, |
| 45 | .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, |
Dennis Wassenberg | bd10516 | 2015-09-10 12:20:58 +0200 | [diff] [blame] | 46 | .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, |
Angel Pons | b21bffa | 2020-07-03 01:02:28 +0200 | [diff] [blame] | 47 | .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, |
Dennis Wassenberg | bd10516 | 2015-09-10 12:20:58 +0200 | [diff] [blame] | 48 | .wdbbar = 0x4000000, |
| 49 | .wdbsize = 0x1000, |
| 50 | .hpet_address = CONFIG_HPET_ADDRESS, |
Angel Pons | 92717ff | 2020-09-14 16:22:22 +0200 | [diff] [blame] | 51 | .rcba = (uintptr_t)DEFAULT_RCBA, |
Dennis Wassenberg | bd10516 | 2015-09-10 12:20:58 +0200 | [diff] [blame] | 52 | .pmbase = DEFAULT_PMBASE, |
| 53 | .gpiobase = DEFAULT_GPIOBASE, |
| 54 | .thermalbase = 0xfed08000, |
| 55 | .system_type = 0, // 0 Mobile, 1 Desktop/Server |
| 56 | .tseg_size = CONFIG_SMM_TSEG_SIZE, |
| 57 | .spd_addresses = { 0xA0, 0xA2, 0xA4, 0xA6 }, |
| 58 | .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, |
| 59 | .ec_present = 1, |
| 60 | .gbe_enable = 1, |
| 61 | .ddr3lv_support = 0, |
Dennis Wassenberg | bd10516 | 2015-09-10 12:20:58 +0200 | [diff] [blame] | 62 | .max_ddr3_freq = 1600, |
| 63 | .usb_port_config = { |
| 64 | /* Enabled / OC PIN / Length */ |
| 65 | { 1, 0, 0x0080 }, /* P00: 1st (left) USB3 (OC #0) */ |
| 66 | { 1, 0, 0x0080 }, /* P01: 2nd (left) USB3 (OC #0) */ |
| 67 | { 1, 1, 0x0080 }, /* P02: 1st Multibay USB3 (OC #1) */ |
| 68 | { 1, 1, 0x0080 }, /* P03: 2nd Multibay USB3 (OC #1) */ |
| 69 | { 1, 8, 0x0040 }, /* P04: MiniPCIe 1 USB2 (no OC) */ |
| 70 | { 1, 8, 0x0040 }, /* P05: MiniPCIe 2 USB2 (no OC) */ |
| 71 | { 1, 8, 0x0040 }, /* P06: USB Hub x4 USB2 (no OC) */ |
| 72 | { 1, 8, 0x0040 }, /* P07: MiniPCIe 4 USB2 (no OC) */ |
| 73 | { 1, 8, 0x0080 }, /* P08: SD card reader USB2 (no OC) */ |
| 74 | { 1, 4, 0x0080 }, /* P09: 3rd (right) USB2 (OC #4) */ |
| 75 | { 1, 5, 0x0040 }, /* P10: 4th (right) USB2 (OC #5) */ |
| 76 | { 1, 8, 0x0040 }, /* P11: 3rd Multibay USB2 (no OC) */ |
| 77 | { 1, 8, 0x0080 }, /* P12: misc internal USB2 (no OC) */ |
| 78 | { 1, 6, 0x0080 }, /* P13: misc internal USB2 (OC #6) */ |
| 79 | }, |
| 80 | .usb3 = { |
| 81 | .mode = 3, /* Smart Auto? */ |
| 82 | .hs_port_switch_mask = 0xf, /* All four ports. */ |
| 83 | .preboot_support = 1, /* preOS driver? */ |
| 84 | .xhci_streams = 1, /* Enable. */ |
| 85 | }, |
| 86 | .pcie_init = 1, |
| 87 | }; |
| 88 | *pei_data = pei_data_template; |
| 89 | } |
| 90 | |
| 91 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
| 92 | /* Enabled / Power / OC PIN */ |
| 93 | { 1, 1, 0 }, /* P00: 1st (left) USB3 (OC #0) */ |
| 94 | { 1, 1, 0 }, /* P01: 2nd (left) USB3 (OC #0) */ |
| 95 | { 1, 1, 1 }, /* P02: 1st Multibay USB3 (OC #1) */ |
| 96 | { 1, 1, 1 }, /* P03: 2nd Multibay USB3 (OC #1) */ |
| 97 | { 1, 0, 8 }, /* P04: MiniPCIe 1 USB2 (no OC) */ |
| 98 | { 1, 0, 8 }, /* P05: MiniPCIe 2 USB2 (no OC) */ |
| 99 | { 1, 0, 8 }, /* P06: USB Hub x4 USB2 (no OC) */ |
| 100 | { 1, 0, 8 }, /* P07: MiniPCIe 4 USB2 (no OC) */ |
| 101 | { 1, 1, 8 }, /* P08: SD card reader USB2 (no OC) */ |
| 102 | { 1, 1, 4 }, /* P09: 3rd (right) USB2 (OC #4) */ |
| 103 | { 1, 0, 5 }, /* P10: 4th (right) USB2 (OC #5) */ |
| 104 | { 1, 0, 8 }, /* P11: 3rd Multibay USB2 (no OC) */ |
| 105 | { 1, 1, 8 }, /* P12: misc internal USB2 (no OC) */ |
| 106 | { 1, 1, 6 }, /* P13: misc internal USB2 (OC #6) */ |
| 107 | }; |
| 108 | |
| 109 | void mainboard_get_spd(spd_raw_data *spd, bool id_only) |
| 110 | { |
| 111 | read_spd(&spd[0], 0x50, id_only); |
| 112 | read_spd(&spd[1], 0x51, id_only); |
| 113 | read_spd(&spd[2], 0x52, id_only); |
| 114 | read_spd(&spd[3], 0x53, id_only); |
| 115 | } |