Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google, Inc. |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 5 | * Copyright (C) 2015 Intel Corp. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
Marshall Dawson | e8c527e | 2017-01-13 14:23:49 -0700 | [diff] [blame] | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 15 | */ |
| 16 | |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 17 | #include <device/pci_ops.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 18 | #include <cpu/x86/cache.h> |
| 19 | #include <cpu/x86/msr.h> |
| 20 | #include <cpu/x86/mtrr.h> |
| 21 | #include <soc/iosf.h> |
| 22 | #include <cpu/intel/microcode/microcode.c> |
| 23 | |
| 24 | static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type) |
| 25 | { |
| 26 | msr_t basem, maskm; |
| 27 | basem.lo = base | type; |
| 28 | basem.hi = 0; |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 29 | wrmsr(MTRR_PHYS_BASE(reg), basem); |
| 30 | maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 31 | maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 32 | wrmsr(MTRR_PHYS_MASK(reg), maskm); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 33 | } |
| 34 | |
| 35 | static void enable_rom_caching(void) |
| 36 | { |
| 37 | msr_t msr; |
| 38 | |
| 39 | disable_cache(); |
| 40 | /* Why only top 4MiB ? */ |
| 41 | set_var_mtrr(1, 0xffc00000, 4*1024*1024, MTRR_TYPE_WRPROT); |
| 42 | enable_cache(); |
| 43 | |
| 44 | /* Enable Variable MTRRs */ |
| 45 | msr.hi = 0x00000000; |
| 46 | msr.lo = 0x00000800; |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 47 | wrmsr(MTRR_DEF_TYPE_MSR, msr); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 48 | } |
| 49 | |
| 50 | static void setup_mmconfig(void) |
| 51 | { |
| 52 | uint32_t reg; |
| 53 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 54 | /* |
| 55 | * Set up the MMCONF range. The register lives in the BUNIT. The |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 56 | * IO variant of the config access needs to be used initially to |
| 57 | * properly configure as the IOSF access registers live in PCI |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 58 | * config space. |
| 59 | */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 60 | reg = 0; |
| 61 | /* Clear the extended register. */ |
| 62 | pci_io_write_config32(IOSF_PCI_DEV, MCRX_REG, reg); |
| 63 | reg = CONFIG_MMCONF_BASE_ADDRESS | 1; |
| 64 | pci_io_write_config32(IOSF_PCI_DEV, MDR_REG, reg); |
| 65 | reg = IOSF_OPCODE(IOSF_OP_WRITE_BUNIT) | IOSF_PORT(IOSF_PORT_BUNIT) | |
| 66 | IOSF_REG(BUNIT_MMCONF_REG) | IOSF_BYTE_EN; |
| 67 | pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg); |
| 68 | } |
| 69 | |
| 70 | static void bootblock_cpu_init(void) |
| 71 | { |
| 72 | /* Allow memory-mapped PCI config access. */ |
| 73 | setup_mmconfig(); |
| 74 | |
| 75 | /* Load microcode before any caching. */ |
| 76 | intel_update_microcode_from_cbfs(); |
| 77 | enable_rom_caching(); |
| 78 | } |