Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011-2013 Alexandru Gagniuc <mr.nuke.me@gmail.com> |
| 5 | * |
| 6 | * This program is free software: you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation, either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | /** |
| 21 | * @file ddr3_util.h |
| 22 | * |
| 23 | * \brief Utilities for decoding DDR3 SPDs |
| 24 | */ |
| 25 | |
| 26 | #include <console/console.h> |
| 27 | #include <device/device.h> |
| 28 | #include <device/dram/ddr3.h> |
| 29 | |
Alexandru Gagniuc | 78706fd | 2013-06-03 13:58:10 -0500 | [diff] [blame] | 30 | /*============================================================================== |
| 31 | * = DDR3 SPD decoding helpers |
| 32 | *----------------------------------------------------------------------------*/ |
| 33 | |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 34 | /** |
| 35 | * \brief Checks if the DIMM is Registered based on byte[3] of the SPD |
| 36 | * |
| 37 | * Tells if the DIMM type is registered or not. |
| 38 | * |
| 39 | * @param type DIMM type. This is byte[3] of the SPD. |
| 40 | */ |
| 41 | int dimm_is_registered(enum spd_dimm_type type) |
| 42 | { |
| 43 | if ((type == SPD_DIMM_TYPE_RDIMM) |
| 44 | | (type == SPD_DIMM_TYPE_MINI_RDIMM) |
| 45 | | (type == SPD_DIMM_TYPE_72B_SO_RDIMM)) |
| 46 | return 1; |
| 47 | |
| 48 | return 0; |
| 49 | } |
| 50 | |
| 51 | /** |
| 52 | * \brief Decode the raw SPD data |
| 53 | * |
| 54 | * Decodes a raw SPD data from a DDR3 DIMM, and organizes it into a |
| 55 | * @ref dimm_attr structure. The SPD data must first be read in a contiguous |
| 56 | * array, and passed to this function. |
| 57 | * |
Martin Roth | 63373ed | 2013-07-08 16:24:19 -0600 | [diff] [blame] | 58 | * @param dimm pointer to @ref dimm_attr structure where the decoded data is to |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 59 | * be stored |
| 60 | * @param spd array of raw data previously read from the SPD. |
| 61 | * |
| 62 | * @return @ref spd_status enumerator |
| 63 | * SPD_STATUS_OK -- decoding was successful |
| 64 | * SPD_STATUS_INVALID -- invalid SPD or not a DDR3 SPD |
| 65 | * SPD_STATUS_CRC_ERROR -- CRC did not verify |
| 66 | * SPD_STATUS_INVALID_FIELD -- A field with an invalid value was |
| 67 | * detected. |
| 68 | */ |
| 69 | int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) |
| 70 | { |
| 71 | int nCRC, i, ret; |
| 72 | u16 crc, spd_crc; |
| 73 | u8 *ptr = spd; |
| 74 | u8 ftb_divisor, ftb_dividend, capacity_shift, bus_width, sdram_width; |
| 75 | u8 reg8; |
| 76 | u32 mtb; /* medium time base */ |
| 77 | unsigned int val, param; |
| 78 | |
| 79 | ret = SPD_STATUS_OK; |
| 80 | |
| 81 | /* Don't assume we memset 0 dimm struct. Clear all our flags */ |
| 82 | dimm->flags.raw = 0; |
| 83 | /* Make sure that the SPD dump is indeed from a DDR3 module */ |
| 84 | if (spd[2] != SPD_MEMORY_TYPE_SDRAM_DDR3) { |
| 85 | printram("Not a DDR3 SPD!\n"); |
| 86 | dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; |
| 87 | return SPD_STATUS_INVALID; |
| 88 | } |
| 89 | dimm->dram_type = SPD_MEMORY_TYPE_SDRAM_DDR3; |
| 90 | |
| 91 | /* Find the number of bytes covered by CRC */ |
| 92 | if (spd[0] & 0x80) { |
| 93 | nCRC = 117; |
| 94 | } else { |
| 95 | nCRC = 126; |
| 96 | } |
| 97 | |
| 98 | /* Compute the CRC */ |
| 99 | crc = 0; |
| 100 | while (--nCRC >= 0) { |
| 101 | crc = crc ^ (int)*ptr++ << 8; |
| 102 | for (i = 0; i < 8; ++i) |
| 103 | if (crc & 0x8000) { |
| 104 | crc = crc << 1 ^ 0x1021; |
| 105 | } else { |
| 106 | crc = crc << 1; |
| 107 | } |
| 108 | } |
| 109 | /* Compare with the CRC in the SPD */ |
| 110 | spd_crc = (spd[127] << 8) + spd[126]; |
| 111 | /* Verify the CRC is correct */ |
| 112 | if (crc != spd_crc) { |
| 113 | printram("ERROR: SPD CRC failed!!!"); |
| 114 | ret = SPD_STATUS_CRC_ERROR; |
| 115 | }; |
| 116 | |
| 117 | printram(" Revision: %x\n", spd[1]); |
| 118 | printram(" Type : %x\n", spd[2]); |
| 119 | printram(" Key : %x\n", spd[3]); |
| 120 | |
| 121 | reg8 = spd[4]; |
| 122 | /* Number of memory banks */ |
| 123 | val = (reg8 >> 4) & 0x07; |
| 124 | if (val > 0x03) { |
| 125 | printram(" Invalid number of memory banks\n"); |
| 126 | ret = SPD_STATUS_INVALID_FIELD; |
| 127 | } |
| 128 | param = 1 << (val + 3); |
| 129 | printram(" Banks : %u\n", param); |
| 130 | /* SDRAM capacity */ |
| 131 | capacity_shift = reg8 & 0x0f; |
| 132 | if (capacity_shift > 0x06) { |
| 133 | printram(" Invalid module capacity\n"); |
| 134 | ret = SPD_STATUS_INVALID_FIELD; |
| 135 | } |
| 136 | if (capacity_shift < 0x02) { |
| 137 | printram(" Capacity: %u Mb\n", 256 << capacity_shift); |
| 138 | } else { |
| 139 | printram(" Capacity: %u Gb\n", 1 << (capacity_shift - 2)); |
| 140 | } |
| 141 | |
| 142 | reg8 = spd[5]; |
| 143 | /* Row address bits */ |
| 144 | val = (reg8 >> 3) & 0x07; |
| 145 | if (val > 0x04) { |
| 146 | printram(" Invalid row address bits\n"); |
| 147 | ret = SPD_STATUS_INVALID_FIELD; |
| 148 | } |
| 149 | dimm->row_bits = val + 12; |
| 150 | /* Column address bits */ |
| 151 | val = reg8 & 0x07; |
| 152 | if (val > 0x03) { |
| 153 | printram(" Invalid column address bits\n"); |
| 154 | ret = SPD_STATUS_INVALID_FIELD; |
| 155 | } |
| 156 | dimm->col_bits = val + 9; |
| 157 | |
| 158 | /* Module nominal voltage */ |
| 159 | reg8 = spd[6]; |
| 160 | printram(" Supported voltages:"); |
| 161 | if (reg8 & (1 << 2)) { |
| 162 | dimm->flags.operable_1_25V = 1; |
| 163 | printram(" 1.25V"); |
| 164 | } |
| 165 | if (reg8 & (1 << 1)) { |
| 166 | dimm->flags.operable_1_35V = 1; |
| 167 | printram(" 1.35V"); |
| 168 | } |
| 169 | if (!(reg8 & (1 << 0))) { |
| 170 | dimm->flags.operable_1_50V = 1; |
| 171 | printram(" 1.5V"); |
| 172 | } |
| 173 | printram("\n"); |
| 174 | |
| 175 | /* Module organization */ |
| 176 | reg8 = spd[7]; |
| 177 | /* Number of ranks */ |
| 178 | val = (reg8 >> 3) & 0x07; |
| 179 | if (val > 3) { |
| 180 | printram(" Invalid number of ranks\n"); |
| 181 | ret = SPD_STATUS_INVALID_FIELD; |
| 182 | } |
| 183 | dimm->ranks = val + 1; |
| 184 | /* SDRAM device width */ |
| 185 | val = (reg8 & 0x07); |
| 186 | if (val > 3) { |
| 187 | printram(" Invalid SDRAM width\n"); |
| 188 | ret = SPD_STATUS_INVALID_FIELD; |
| 189 | } |
| 190 | sdram_width = (4 << val); |
| 191 | printram(" SDRAM width : %u\n", sdram_width); |
| 192 | |
| 193 | /* Memory bus width */ |
| 194 | reg8 = spd[8]; |
| 195 | /* Bus extension */ |
| 196 | val = (reg8 >> 3) & 0x03; |
| 197 | if (val > 1) { |
| 198 | printram(" Invalid bus extension\n"); |
| 199 | ret = SPD_STATUS_INVALID_FIELD; |
| 200 | } |
| 201 | dimm->flags.is_ecc = val ? 1 : 0; |
| 202 | printram(" Bus extension : %u bits\n", val ? 8 : 0); |
| 203 | /* Bus width */ |
| 204 | val = reg8 & 0x07; |
| 205 | if (val > 3) { |
| 206 | printram(" Invalid bus width\n"); |
| 207 | ret = SPD_STATUS_INVALID_FIELD; |
| 208 | } |
| 209 | bus_width = 8 << val; |
| 210 | printram(" Bus width : %u\n", bus_width); |
| 211 | |
| 212 | /* We have all the info we need to compute the dimm size */ |
| 213 | /* Capacity is 256Mbit multiplied by the power of 2 specified in |
| 214 | * capacity_shift |
| 215 | * The rest is the JEDEC formula */ |
| 216 | dimm->size_mb = ((1 << (capacity_shift + (25 - 20))) * bus_width |
| 217 | * dimm->ranks) / sdram_width; |
| 218 | |
| 219 | /* Fine Timebase (FTB) Dividend/Divisor */ |
| 220 | /* Dividend */ |
| 221 | ftb_dividend = (spd[9] >> 4) & 0x0f; |
| 222 | /* Divisor */ |
| 223 | ftb_divisor = spd[9] & 0x0f; |
| 224 | |
| 225 | /* Medium Timebase = |
| 226 | * Medium Timebase (MTB) Dividend / |
| 227 | * Medium Timebase (MTB) Divisor */ |
| 228 | mtb = (((u32) spd[10]) << 8) / spd[11]; |
| 229 | |
| 230 | /* SDRAM Minimum Cycle Time (tCKmin) */ |
| 231 | dimm->tCK = spd[12] * mtb; |
| 232 | /* CAS Latencies Supported */ |
| 233 | dimm->cas_supported = (spd[15] << 8) + spd[14]; |
| 234 | /* Minimum CAS Latency Time (tAAmin) */ |
| 235 | dimm->tAA = spd[16] * mtb; |
| 236 | /* Minimum Write Recovery Time (tWRmin) */ |
| 237 | dimm->tWR = spd[17] * mtb; |
| 238 | /* Minimum RAS# to CAS# Delay Time (tRCDmin) */ |
| 239 | dimm->tRCD = spd[18] * mtb; |
| 240 | /* Minimum Row Active to Row Active Delay Time (tRRDmin) */ |
| 241 | dimm->tRRD = spd[19] * mtb; |
| 242 | /* Minimum Row Precharge Delay Time (tRPmin) */ |
| 243 | dimm->tRP = spd[20] * mtb; |
| 244 | /* Minimum Active to Precharge Delay Time (tRASmin) */ |
| 245 | dimm->tRAS = (((spd[21] & 0x0f) << 8) + spd[22]) * mtb; |
| 246 | /* Minimum Active to Active/Refresh Delay Time (tRCmin) */ |
| 247 | dimm->tRC = (((spd[21] & 0xf0) << 4) + spd[23]) * mtb; |
| 248 | /* Minimum Refresh Recovery Delay Time (tRFCmin) */ |
| 249 | dimm->tRFC = ((spd[25] << 8) + spd[24]) * mtb; |
| 250 | /* Minimum Internal Write to Read Command Delay Time (tWTRmin) */ |
| 251 | dimm->tWTR = spd[26] * mtb; |
| 252 | /* Minimum Internal Read to Precharge Command Delay Time (tRTPmin) */ |
| 253 | dimm->tRTP = spd[27] * mtb; |
| 254 | /* Minimum Four Activate Window Delay Time (tFAWmin) */ |
| 255 | dimm->tFAW = (((spd[28] & 0x0f) << 8) + spd[29]) * mtb; |
| 256 | |
| 257 | /* SDRAM Optional Features */ |
| 258 | reg8 = spd[30]; |
| 259 | printram(" Optional features :"); |
| 260 | if (reg8 & 0x80) { |
| 261 | dimm->flags.dll_off_mode = 1; |
| 262 | printram(" DLL-Off_mode"); |
| 263 | } |
| 264 | if (reg8 & 0x02) { |
| 265 | dimm->flags.rzq7_supported = 1; |
| 266 | printram(" RZQ/7"); |
| 267 | } |
| 268 | if (reg8 & 0x01) { |
| 269 | dimm->flags.rzq6_supported = 1; |
| 270 | printram(" RZQ/6"); |
| 271 | } |
| 272 | printram("\n"); |
| 273 | |
| 274 | /* SDRAM Thermal and Refresh Options */ |
| 275 | reg8 = spd[31]; |
| 276 | printram(" Thermal features :"); |
| 277 | if (reg8 & 0x80) { |
| 278 | dimm->flags.pasr = 1; |
| 279 | printram(" PASR"); |
| 280 | } |
| 281 | if (reg8 & 0x08) { |
| 282 | dimm->flags.odts = 1; |
| 283 | printram(" ODTS"); |
| 284 | } |
| 285 | if (reg8 & 0x04) { |
| 286 | dimm->flags.asr = 1; |
| 287 | printram(" ASR"); |
| 288 | } |
| 289 | if (reg8 & 0x02) { |
| 290 | dimm->flags.ext_temp_range = 1; |
| 291 | printram(" ext_temp_refresh"); |
| 292 | } |
| 293 | if (reg8 & 0x01) { |
| 294 | dimm->flags.ext_temp_refresh = 1; |
| 295 | printram(" ext_temp_range"); |
| 296 | } |
| 297 | printram("\n"); |
| 298 | |
| 299 | /* Module Thermal Sensor */ |
| 300 | reg8 = spd[32]; |
| 301 | if (reg8 & 0x80) |
| 302 | dimm->flags.therm_sensor = 1; |
| 303 | printram(" Thermal sensor : %s\n", |
| 304 | dimm->flags.therm_sensor ? "yes" : "no"); |
| 305 | |
| 306 | /* SDRAM Device Type */ |
| 307 | reg8 = spd[33]; |
| 308 | printram(" Standard SDRAM : %s\n", (reg8 & 0x80) ? "no" : "yes"); |
| 309 | |
| 310 | if (spd[63] & 0x01) { |
| 311 | dimm->flags.pins_mirrored = 1; |
Martin Roth | 63373ed | 2013-07-08 16:24:19 -0600 | [diff] [blame] | 312 | printram(" DIMM Rank1 Address bits mirrored!!!\n"); |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 313 | } |
| 314 | |
| 315 | return ret; |
| 316 | } |
| 317 | |
| 318 | /* |
| 319 | * The information printed below has a more informational character, and is not |
| 320 | * necessarily tied in to RAM init debugging. Hence, we stop using printram(), |
| 321 | * and use the standard printk()'s below. |
| 322 | */ |
| 323 | |
| 324 | static void print_ns(const char *msg, u32 val) |
| 325 | { |
| 326 | u32 mant, fp; |
| 327 | mant = val / 256; |
| 328 | fp = (val % 256) * 1000 / 256; |
| 329 | |
| 330 | printk(BIOS_INFO, "%s%3u.%.3u ns\n", msg, mant, fp); |
| 331 | } |
| 332 | |
| 333 | /** |
| 334 | * \brief Print the info in DIMM |
| 335 | * |
| 336 | * Print info about the DIMM. Useful to use when CONFIG_DEBUG_RAM_SETUP is |
| 337 | * selected, or for a purely informative output. |
| 338 | * |
Martin Roth | 63373ed | 2013-07-08 16:24:19 -0600 | [diff] [blame] | 339 | * @param dimm pointer to already decoded @ref dimm_attr structure |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 340 | */ |
| 341 | void dram_print_spd_ddr3(const dimm_attr * dimm) |
| 342 | { |
| 343 | u16 val16; |
| 344 | int i; |
| 345 | |
| 346 | printk(BIOS_INFO, " Row addr bits : %u\n", dimm->row_bits); |
| 347 | printk(BIOS_INFO, " Column addr bits : %u\n", dimm->col_bits); |
| 348 | printk(BIOS_INFO, " Number of ranks : %u\n", dimm->ranks); |
| 349 | printk(BIOS_INFO, " DIMM Capacity : %u MB\n", dimm->size_mb); |
| 350 | |
| 351 | /* CAS Latencies Supported */ |
| 352 | val16 = dimm->cas_supported; |
| 353 | printk(BIOS_INFO, " CAS latencies :"); |
| 354 | i = 0; |
| 355 | do { |
| 356 | if (val16 & 1) |
| 357 | printk(BIOS_INFO, " %u", i + 4); |
| 358 | i++; |
| 359 | val16 >>= 1; |
| 360 | } while (val16); |
| 361 | printk(BIOS_INFO, "\n"); |
| 362 | |
| 363 | print_ns(" tCKmin : ", dimm->tCK); |
| 364 | print_ns(" tAAmin : ", dimm->tAA); |
| 365 | print_ns(" tWRmin : ", dimm->tWR); |
| 366 | print_ns(" tRCDmin : ", dimm->tRCD); |
| 367 | print_ns(" tRRDmin : ", dimm->tRRD); |
| 368 | print_ns(" tRPmin : ", dimm->tRP); |
| 369 | print_ns(" tRASmin : ", dimm->tRAS); |
| 370 | print_ns(" tRCmin : ", dimm->tRC); |
| 371 | print_ns(" tRFCmin : ", dimm->tRFC); |
| 372 | print_ns(" tWTRmin : ", dimm->tWTR); |
| 373 | print_ns(" tRTPmin : ", dimm->tRTP); |
| 374 | print_ns(" tFAWmin : ", dimm->tFAW); |
Alexandru Gagniuc | 78706fd | 2013-06-03 13:58:10 -0500 | [diff] [blame] | 375 | } |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 376 | |
Alexandru Gagniuc | 78706fd | 2013-06-03 13:58:10 -0500 | [diff] [blame] | 377 | /*============================================================================== |
| 378 | *= DDR3 MRS helpers |
| 379 | *----------------------------------------------------------------------------*/ |
| 380 | |
| 381 | /* |
| 382 | * MRS command structure: |
| 383 | * cmd[15:0] = Address pins MA[15:0] |
| 384 | * cmd[18:16] = Bank address BA[2:0] |
| 385 | */ |
| 386 | |
| 387 | /* Map tWR value to a bitmask of the MR0 cycle */ |
| 388 | static u16 ddr3_twr_to_mr0_map(u8 twr) |
| 389 | { |
| 390 | if ((twr >= 5) && (twr <= 8)) |
| 391 | return (twr - 4) << 9; |
| 392 | |
| 393 | /* |
| 394 | * From 8T onwards, we can only use even values. Round up if we are |
| 395 | * given an odd value. |
| 396 | */ |
| 397 | if ((twr >= 9) && (twr <= 14)) |
| 398 | return ((twr + 1) >> 1) << 9; |
| 399 | |
| 400 | /* tWR == 16T is [000] */ |
| 401 | return 0; |
| 402 | } |
| 403 | |
| 404 | /* Map the CAS latency to a bitmask for the MR0 cycle */ |
| 405 | static u16 ddr3_cas_to_mr0_map(u8 cas) |
| 406 | { |
| 407 | u16 mask = 0; |
| 408 | /* A[6:4] are bits [2:0] of (CAS - 4) */ |
| 409 | mask = ((cas - 4) & 0x07) << 4; |
| 410 | |
| 411 | /* A2 is the MSB of (CAS - 4) */ |
| 412 | if ((cas - 4) & (1 << 3)) |
| 413 | mask |= (1 << 2); |
| 414 | |
| 415 | return mask; |
| 416 | } |
| 417 | |
| 418 | /** |
| 419 | * \brief Get command address for a DDR3 MR0 command |
| 420 | * |
| 421 | * The DDR3 specification only covers odd write_recovery up to 7T. If an odd |
| 422 | * write_recovery greater than 7 is specified, it will be rounded up. If a tWR |
| 423 | * greater than 8 is specified, it is recommended to explicitly round it up or |
| 424 | * down before calling this function. |
| 425 | * |
| 426 | * write_recovery and cas are given in clock cycles. For example, a CAS of 7T |
| 427 | * should be given as 7. |
| 428 | * |
| 429 | * @param write_recovery Write recovery latency, tWR in clock cycles. |
| 430 | * @param cas CAS latency in clock cycles. |
| 431 | */ |
| 432 | mrs_cmd_t ddr3_get_mr0(enum ddr3_mr0_precharge precharge_pd, |
| 433 | u8 write_recovery, |
| 434 | enum ddr3_mr0_dll_reset dll_reset, |
| 435 | enum ddr3_mr0_mode mode, |
| 436 | u8 cas, |
| 437 | enum ddr3_mr0_burst_type burst_type, |
| 438 | enum ddr3_mr0_burst_length burst_length) |
| 439 | { |
| 440 | mrs_cmd_t cmd = 0 << 16; |
| 441 | |
| 442 | if (precharge_pd == DDR3_MR0_PRECHARGE_FAST) |
| 443 | cmd |= (1 << 12); |
| 444 | |
| 445 | cmd |= ddr3_twr_to_mr0_map(write_recovery); |
| 446 | |
| 447 | if (dll_reset == DDR3_MR0_DLL_RESET_YES) |
| 448 | cmd |= (1 << 8); |
| 449 | |
| 450 | if (mode == DDR3_MR0_MODE_TEST) |
| 451 | cmd |= (1 << 7); |
| 452 | |
| 453 | cmd |= ddr3_cas_to_mr0_map(cas); |
| 454 | |
| 455 | if (burst_type == DDR3_MR0_BURST_TYPE_INTERLEAVED) |
| 456 | cmd |= (1 << 3); |
| 457 | |
| 458 | cmd |= (burst_length & 0x03) << 0; |
| 459 | |
| 460 | return cmd; |
| 461 | } |
| 462 | |
| 463 | static u16 ddr3_rtt_nom_to_mr1_map(enum ddr3_mr1_rtt_nom rtt_nom) |
| 464 | { |
| 465 | u16 mask = 0; |
| 466 | /* A9 <-> rtt_nom[2] */ |
| 467 | if (rtt_nom & (1 << 2)) |
| 468 | mask |= (1 << 9); |
| 469 | /* A6 <-> rtt_nom[1] */ |
| 470 | if (rtt_nom & (1 << 1)) |
| 471 | mask |= (1 << 6); |
| 472 | /* A2 <-> rtt_nom[0] */ |
| 473 | if (rtt_nom & (1 << 0)) |
| 474 | mask |= (1 << 2); |
| 475 | |
| 476 | return mask; |
| 477 | } |
| 478 | |
| 479 | static u16 ddr3_ods_to_mr1_map(enum ddr3_mr1_ods ods) |
| 480 | { |
| 481 | u16 mask = 0; |
| 482 | /* A5 <-> ods[1] */ |
| 483 | if (ods & (1 << 1)) |
| 484 | mask |= (1 << 5); |
| 485 | /* A1 <-> ods[0] */ |
| 486 | if (ods & (1 << 0)) |
| 487 | mask |= (1 << 1); |
| 488 | |
| 489 | return mask; |
| 490 | } |
| 491 | |
| 492 | /** |
| 493 | * \brief Get command address for a DDR3 MR1 command |
| 494 | */ |
| 495 | mrs_cmd_t ddr3_get_mr1(enum ddr3_mr1_qoff qoff, |
| 496 | enum ddr3_mr1_tqds tqds, |
| 497 | enum ddr3_mr1_rtt_nom rtt_nom, |
| 498 | enum ddr3_mr1_write_leveling write_leveling, |
| 499 | enum ddr3_mr1_ods ods, |
| 500 | enum ddr3_mr1_additive_latency additive_latency, |
| 501 | enum ddr3_mr1_dll dll_disable) |
| 502 | { |
| 503 | mrs_cmd_t cmd = 1 << 16; |
| 504 | |
| 505 | if (qoff == DDR3_MR1_QOFF_DISABLE) |
| 506 | cmd |= (1 << 12); |
| 507 | |
| 508 | if (tqds == DDR3_MR1_TQDS_ENABLE) |
| 509 | cmd |= (1 << 11); |
| 510 | |
| 511 | cmd |= ddr3_rtt_nom_to_mr1_map(rtt_nom); |
| 512 | |
| 513 | if (write_leveling == DDR3_MR1_WRLVL_ENABLE) |
| 514 | cmd |= (1 << 7); |
| 515 | |
| 516 | cmd |= ddr3_ods_to_mr1_map(ods); |
| 517 | |
| 518 | cmd |= (additive_latency & 0x03) << 3; |
| 519 | |
| 520 | if (dll_disable == DDR3_MR1_DLL_DISABLE) |
| 521 | cmd |= (1 << 0); |
| 522 | |
| 523 | return cmd; |
| 524 | } |
| 525 | |
| 526 | /** |
| 527 | * \brief Get command address for a DDR3 MR2 command |
| 528 | * |
| 529 | * cas_cwl is given in clock cycles. For example, a cas_cwl of 7T should be |
| 530 | * given as 7. |
| 531 | * |
| 532 | * @param cas_cwl CAS write latency in clock cycles. |
| 533 | */ |
| 534 | mrs_cmd_t ddr3_get_mr2(enum ddr3_mr2_rttwr rtt_wr, |
| 535 | enum ddr3_mr2_srt_range extended_temp, |
| 536 | enum ddr3_mr2_asr self_refresh, u8 cas_cwl) |
| 537 | { |
| 538 | mrs_cmd_t cmd = 2 << 16; |
| 539 | |
| 540 | cmd |= (rtt_wr & 0x03) << 9; |
| 541 | |
| 542 | if (extended_temp == DDR3_MR2_SRT_EXTENDED) |
| 543 | cmd |= (1 << 7); |
| 544 | |
| 545 | if (self_refresh == DDR3_MR2_ASR_AUTO) |
| 546 | cmd |= (1 << 6); |
| 547 | |
| 548 | cmd |= ((cas_cwl - 5) & 0x07) << 3; |
| 549 | |
| 550 | return cmd; |
| 551 | } |
| 552 | |
| 553 | /** |
| 554 | * \brief Get command address for a DDR3 MR3 command |
| 555 | * |
| 556 | * @param dataflow_from_mpr Specify a non-zero value to put DRAM in read |
| 557 | * leveling mode. Zero for normal operation. |
| 558 | */ |
| 559 | mrs_cmd_t ddr3_get_mr3(char dataflow_from_mpr) |
| 560 | { |
| 561 | mrs_cmd_t cmd = 3 << 16; |
| 562 | |
| 563 | if (dataflow_from_mpr) |
| 564 | cmd |= (1 << 2); |
| 565 | |
| 566 | return cmd; |
| 567 | } |
| 568 | |
| 569 | /** |
| 570 | * \brief Mirror the address bits for this MRS command |
| 571 | * |
| 572 | * Swap the following bits in the MRS command: |
| 573 | * - MA3 <-> MA4 |
| 574 | * - MA5 <-> MA6 |
| 575 | * - MA7 <-> MA8 |
| 576 | * - BA0 <-> BA1 |
| 577 | */ |
| 578 | mrs_cmd_t ddr3_mrs_mirror_pins(mrs_cmd_t cmd) |
| 579 | { |
| 580 | u32 downshift, upshift; |
| 581 | /* High bits= A4 | A6 | A8 | BA1 */ |
| 582 | /* Low bits = A3 | A5 | A7 | BA0 */ |
| 583 | u32 lowbits = (1 << 3) | (1 << 5) | (1 << 7) | (1 << 16); |
| 584 | downshift = (cmd & (lowbits << 1)); |
| 585 | upshift = (cmd & lowbits); |
| 586 | cmd &= ~(lowbits | (lowbits << 1)); |
| 587 | cmd |= (downshift >> 1) | (upshift << 1); |
| 588 | return cmd; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 589 | } |