Wang Qing Pei | 3f90125 | 2010-08-17 11:08:31 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Wang Qing Pei <wangqingpei@gmail.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | //#define SYSTEM_TYPE 0 /* SERVER */ |
| 21 | #define SYSTEM_TYPE 1 /* DESKTOP */ |
| 22 | //#define SYSTEM_TYPE 2 /* MOBILE */ |
| 23 | |
Wang Qing Pei | 3f90125 | 2010-08-17 11:08:31 +0000 | [diff] [blame] | 24 | #include <stdint.h> |
| 25 | #include <string.h> |
| 26 | #include <device/pci_def.h> |
| 27 | #include <device/pci_ids.h> |
| 28 | #include <arch/io.h> |
| 29 | #include <device/pnp_def.h> |
| 30 | #include <arch/romcc_io.h> |
| 31 | #include <cpu/x86/lapic.h> |
| 32 | #include <console/console.h> |
Wang Qing Pei | 3f90125 | 2010-08-17 11:08:31 +0000 | [diff] [blame] | 33 | #include <cpu/amd/model_10xxx_rev.h> |
| 34 | #include "northbridge/amd/amdfam10/raminit.h" |
| 35 | #include "northbridge/amd/amdfam10/amdfam10.h" |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 36 | #include <lib.h> |
Wang Qing Pei | 3f90125 | 2010-08-17 11:08:31 +0000 | [diff] [blame] | 37 | #include "cpu/x86/lapic/boot_cpu.c" |
| 38 | #include "northbridge/amd/amdfam10/reset_test.c" |
Wang Qing Pei | 3f90125 | 2010-08-17 11:08:31 +0000 | [diff] [blame] | 39 | #include <console/loglevel.h> |
| 40 | #include "cpu/x86/bist.h" |
stepan | 8301d83 | 2010-12-08 07:07:33 +0000 | [diff] [blame] | 41 | #include "superio/ite/it8718f/early_serial.c" |
Patrick Georgi | 5692c57 | 2010-10-05 13:40:31 +0000 | [diff] [blame] | 42 | #include <usbdebug.h> |
Wang Qing Pei | 3f90125 | 2010-08-17 11:08:31 +0000 | [diff] [blame] | 43 | #include "cpu/x86/mtrr/earlymtrr.c" |
| 44 | #include <cpu/amd/mtrr.h> |
| 45 | #include "northbridge/amd/amdfam10/setup_resource_map.c" |
stepan | 836ae29 | 2010-12-08 05:42:47 +0000 | [diff] [blame] | 46 | #include "southbridge/amd/rs780/early_setup.c" |
| 47 | #include "southbridge/amd/sb700/early_setup.c" |
Wang Qing Pei | 3f90125 | 2010-08-17 11:08:31 +0000 | [diff] [blame] | 48 | #include "northbridge/amd/amdfam10/debug.c" |
| 49 | |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 50 | static void activate_spd_rom(const struct mem_controller *ctrl) { } |
Wang Qing Pei | 3f90125 | 2010-08-17 11:08:31 +0000 | [diff] [blame] | 51 | |
| 52 | static int spd_read_byte(u32 device, u32 address) |
| 53 | { |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 54 | return smbus_read_byte(device, address); |
Wang Qing Pei | 3f90125 | 2010-08-17 11:08:31 +0000 | [diff] [blame] | 55 | } |
| 56 | |
| 57 | #include "northbridge/amd/amdfam10/amdfam10.h" |
Wang Qing Pei | 3f90125 | 2010-08-17 11:08:31 +0000 | [diff] [blame] | 58 | #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" |
stepan | 8301d83 | 2010-12-08 07:07:33 +0000 | [diff] [blame] | 59 | #include "northbridge/amd/amdfam10/pci.c" |
Wang Qing Pei | 3f90125 | 2010-08-17 11:08:31 +0000 | [diff] [blame] | 60 | #include "resourcemap.c" |
| 61 | #include "cpu/amd/quadcore/quadcore.c" |
Wang Qing Pei | 3f90125 | 2010-08-17 11:08:31 +0000 | [diff] [blame] | 62 | #include "cpu/amd/car/post_cache_as_ram.c" |
| 63 | #include "cpu/amd/microcode/microcode.c" |
Xavi Drudis Ferran | 4c28a6f | 2011-02-26 23:29:44 +0000 | [diff] [blame^] | 64 | |
| 65 | #if CONFIG_UPDATE_CPU_MICROCODE |
Wang Qing Pei | 3f90125 | 2010-08-17 11:08:31 +0000 | [diff] [blame] | 66 | #include "cpu/amd/model_10xxx/update_microcode.c" |
Xavi Drudis Ferran | 4c28a6f | 2011-02-26 23:29:44 +0000 | [diff] [blame^] | 67 | #endif |
| 68 | |
Wang Qing Pei | 3f90125 | 2010-08-17 11:08:31 +0000 | [diff] [blame] | 69 | #include "cpu/amd/model_10xxx/init_cpus.c" |
Wang Qing Pei | 3f90125 | 2010-08-17 11:08:31 +0000 | [diff] [blame] | 70 | #include "northbridge/amd/amdfam10/early_ht.c" |
Patrick Georgi | 9bd9a90 | 2010-11-20 10:31:00 +0000 | [diff] [blame] | 71 | #include <spd.h> |
Wang Qing Pei | 3f90125 | 2010-08-17 11:08:31 +0000 | [diff] [blame] | 72 | |
Wang Qing Pei | 3f90125 | 2010-08-17 11:08:31 +0000 | [diff] [blame] | 73 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
| 74 | { |
Wang Qing Pei | 3f90125 | 2010-08-17 11:08:31 +0000 | [diff] [blame] | 75 | struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); |
| 76 | static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 77 | u32 bsp_apicid = 0, val; |
Wang Qing Pei | 3f90125 | 2010-08-17 11:08:31 +0000 | [diff] [blame] | 78 | msr_t msr; |
| 79 | |
| 80 | if (!cpu_init_detectedx && boot_cpu()) { |
| 81 | /* Nothing special needs to be done to find bus 0 */ |
| 82 | /* Allow the HT devices to be found */ |
| 83 | /* mov bsp to bus 0xff when > 8 nodes */ |
| 84 | set_bsp_node_CHtExtNodeCfgEn(); |
| 85 | enumerate_ht_chain(); |
Wang Qing Pei | 3f90125 | 2010-08-17 11:08:31 +0000 | [diff] [blame] | 86 | sb700_pci_port80(); |
| 87 | } |
| 88 | |
| 89 | post_code(0x30); |
| 90 | |
| 91 | if (bist == 0) { |
| 92 | bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */ |
| 93 | /* All cores run this but the BSP(node0,core0) is the only core that returns. */ |
| 94 | } |
| 95 | |
| 96 | post_code(0x32); |
| 97 | |
| 98 | enable_rs780_dev8(); |
| 99 | sb700_lpc_init(); |
| 100 | |
| 101 | it8718f_enable_serial(0, CONFIG_TTYS0_BASE); |
| 102 | it8718f_disable_reboot(); |
| 103 | uart_init(); |
Uwe Hermann | b015d02 | 2010-09-24 18:18:20 +0000 | [diff] [blame] | 104 | |
| 105 | #if CONFIG_USBDEBUG |
Uwe Hermann | ae3f2b3 | 2010-10-02 20:36:26 +0000 | [diff] [blame] | 106 | sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); |
Uwe Hermann | b015d02 | 2010-09-24 18:18:20 +0000 | [diff] [blame] | 107 | early_usbdebug_init(); |
| 108 | #endif |
| 109 | |
Wang Qing Pei | 3f90125 | 2010-08-17 11:08:31 +0000 | [diff] [blame] | 110 | console_init(); |
| 111 | printk(BIOS_DEBUG, "\n"); |
| 112 | |
| 113 | // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); |
| 114 | |
| 115 | /* Halt if there was a built in self test failure */ |
| 116 | report_bist_failure(bist); |
| 117 | |
| 118 | // Load MPB |
| 119 | val = cpuid_eax(1); |
| 120 | printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); |
| 121 | printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); |
| 122 | printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid); |
| 123 | printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); |
| 124 | |
| 125 | /* Setup sysinfo defaults */ |
| 126 | set_sysinfo_in_ram(0); |
| 127 | |
Xavi Drudis Ferran | 4c28a6f | 2011-02-26 23:29:44 +0000 | [diff] [blame^] | 128 | #if CONFIG_UPDATE_CPU_MICROCODE |
Wang Qing Pei | 3f90125 | 2010-08-17 11:08:31 +0000 | [diff] [blame] | 129 | update_microcode(val); |
Xavi Drudis Ferran | 4c28a6f | 2011-02-26 23:29:44 +0000 | [diff] [blame^] | 130 | #endif |
Wang Qing Pei | 3f90125 | 2010-08-17 11:08:31 +0000 | [diff] [blame] | 131 | post_code(0x33); |
| 132 | |
| 133 | cpuSetAMDMSR(); |
| 134 | post_code(0x34); |
| 135 | |
| 136 | amd_ht_init(sysinfo); |
| 137 | post_code(0x35); |
| 138 | |
| 139 | /* Setup nodes PCI space and start core 0 AP init. */ |
| 140 | finalize_node_setup(sysinfo); |
| 141 | |
| 142 | /* Setup any mainboard PCI settings etc. */ |
| 143 | setup_mb_resource_map(); |
| 144 | post_code(0x36); |
| 145 | |
| 146 | /* wait for all the APs core0 started by finalize_node_setup. */ |
| 147 | /* FIXME: A bunch of cores are going to start output to serial at once. |
| 148 | It would be nice to fixup prink spinlocks for ROM XIP mode. |
| 149 | I think it could be done by putting the spinlock flag in the cache |
| 150 | of the BSP located right after sysinfo. |
| 151 | */ |
| 152 | wait_all_core0_started(); |
| 153 | |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 154 | #if CONFIG_LOGICAL_CPUS==1 |
Wang Qing Pei | 3f90125 | 2010-08-17 11:08:31 +0000 | [diff] [blame] | 155 | /* Core0 on each node is configured. Now setup any additional cores. */ |
| 156 | printk(BIOS_DEBUG, "start_other_cores()\n"); |
| 157 | start_other_cores(); |
| 158 | post_code(0x37); |
| 159 | wait_all_other_cores_started(bsp_apicid); |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 160 | #endif |
Wang Qing Pei | 3f90125 | 2010-08-17 11:08:31 +0000 | [diff] [blame] | 161 | |
| 162 | post_code(0x38); |
| 163 | |
| 164 | /* run _early_setup before soft-reset. */ |
| 165 | rs780_early_setup(); |
| 166 | sb700_early_setup(); |
| 167 | |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 168 | #if CONFIG_SET_FIDVID |
Wang Qing Pei | 3f90125 | 2010-08-17 11:08:31 +0000 | [diff] [blame] | 169 | msr = rdmsr(0xc0010071); |
| 170 | printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); |
| 171 | |
| 172 | /* FIXME: The sb fid change may survive the warm reset and only |
| 173 | need to be done once.*/ |
| 174 | enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); |
| 175 | |
| 176 | post_code(0x39); |
| 177 | |
| 178 | if (!warm_reset_detect(0)) { // BSP is node 0 |
| 179 | init_fidvid_bsp(bsp_apicid, sysinfo->nodes); |
| 180 | } else { |
| 181 | init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 |
| 182 | } |
| 183 | |
| 184 | post_code(0x3A); |
| 185 | |
| 186 | /* show final fid and vid */ |
| 187 | msr=rdmsr(0xc0010071); |
| 188 | printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 189 | #endif |
Wang Qing Pei | 3f90125 | 2010-08-17 11:08:31 +0000 | [diff] [blame] | 190 | |
| 191 | rs780_htinit(); |
| 192 | |
| 193 | /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ |
| 194 | if (!warm_reset_detect(0)) { |
| 195 | print_info("...WARM RESET...\n\n\n"); |
| 196 | soft_reset(); |
| 197 | die("After soft_reset_x - shouldn't see this message!!!\n"); |
| 198 | } |
| 199 | |
| 200 | post_code(0x3B); |
| 201 | |
| 202 | /* It's the time to set ctrl in sysinfo now; */ |
| 203 | printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); |
| 204 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); |
| 205 | |
| 206 | post_code(0x40); |
| 207 | |
| 208 | // die("Die Before MCT init."); |
| 209 | |
| 210 | printk(BIOS_DEBUG, "raminit_amdmct()\n"); |
| 211 | raminit_amdmct(sysinfo); |
| 212 | post_code(0x41); |
| 213 | |
| 214 | /* |
| 215 | dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); |
| 216 | dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); |
| 217 | dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); |
| 218 | dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); |
| 219 | */ |
| 220 | |
Wang Qing Pei | 3f90125 | 2010-08-17 11:08:31 +0000 | [diff] [blame] | 221 | // die("After MCT init before CAR disabled."); |
| 222 | |
| 223 | rs780_before_pci_init(); |
| 224 | sb700_before_pci_init(); |
| 225 | |
| 226 | post_code(0x42); |
| 227 | printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); |
| 228 | post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. |
| 229 | post_code(0x43); // Should never see this post code. |
| 230 | } |