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Stefan Reinauer9fe20cb2012-12-07 17:18:43 -08001# Warning: This file is included whether or not the if is here.
2# The if controls how the evaluation occurs.
3# (See also src/Kconfig)
Stefan Reinauer9fe20cb2012-12-07 17:18:43 -08004
Stefan Reinauera48ca842015-04-04 01:58:28 +02005source "src/cpu/*/Kconfig"
Patrick Georgi0588d192009-08-12 15:00:51 +00006
Furquan Shaikhfd337812014-04-22 15:16:54 -07007if ARCH_X86
Stefan Reinauer704b5962010-08-30 17:53:13 +00009config CACHE_AS_RAM
Patrick Georgi39ec29c2009-08-27 12:10:50 +000010 bool
Stefan Reinauer314e5512010-04-09 20:36:29 +000011 default !ROMCC
Patrick Georgi39ec29c2009-08-27 12:10:50 +000012
Patrick Georgi0588d192009-08-12 15:00:51 +000013config DCACHE_RAM_BASE
14 hex
Patrick Georgi0588d192009-08-12 15:00:51 +000015
17 hex
Patrick Georgi0588d192009-08-12 15:00:51 +000018
Timothy Pearsonb5e46552015-06-02 13:47:36 -050019config DCACHE_BSP_STACK_SIZE
20 hex
Timothy Pearsonfb39f822015-06-02 20:25:03 -050022config DCACHE_BSP_STACK_SLUSH
23 hex
Timothy Pearsonb5e46552015-06-02 13:47:36 -050025config DCACHE_AP_STACK_SIZE
26 hex
Patrick Georgi0588d192009-08-12 15:00:51 +000028config SMP
29 bool
Myles Watson45bb25f2009-09-22 18:49:08 +000030 default y if MAX_CPUS != 1
Patrick Georgi892b0912009-09-24 09:03:06 +000031 default n
Uwe Hermanna29ad5c2009-10-18 18:35:50 +000032 help
33 This option is used to enable certain functions to make coreboot
34 work correctly on symmetric multi processor (SMP) systems.
Ronald G. Minnich149d6752009-10-01 23:22:50 +000035
Kyösti Mälkki7dfe32c2012-02-14 10:39:17 +020036config AP_SIPI_VECTOR
37 hex
38 default 0xfffff000
39 help
40 This must equal address of ap_sipi_vector from bootblock build.
Patrick Georgi819c7d42012-03-31 13:08:12 +020041
Ronald G. Minnich149d6752009-10-01 23:22:50 +000042config MMX
43 bool
Stefan Reinauera7acc512010-02-25 13:40:49 +000044 help
45 Select MMX in your socket or model Kconfig if your CPU has MMX
46 streaming SIMD instructions. ROMCC can build more efficient
47 code if it can spill to MMX registers.
Ronald G. Minnich149d6752009-10-01 23:22:50 +000048
49config SSE
50 bool
Stefan Reinauera7acc512010-02-25 13:40:49 +000051 help
52 Select SSE in your socket or model Kconfig if your CPU has SSE
53 streaming SIMD instructions. ROMCC can build more efficient
54 code if it can spill to SSE (aka XMM) registers.
56config SSE2
57 bool
Myles Watson34261952010-03-19 02:33:40 +000058 default n
Stefan Reinauera7acc512010-02-25 13:40:49 +000059 help
60 Select SSE2 in your socket or model Kconfig if your CPU has SSE2
61 streaming SIMD instructions. Some parts of coreboot can be built
62 with more efficient code if SSE2 instructions are available.
Patrick Georgi0e9a9252009-10-06 20:48:07 +000063
Stefan Reinauer8aedcbc2010-12-16 23:37:17 +000064endif # ARCH_X86
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -050065
Alexandru Gagniuc66e0c4c2013-12-04 22:21:15 -060066config SUPPORT_CPU_UCODE_IN_CBFS
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -050067 bool
68 default n
Martin Roth4c502692015-11-05 08:03:45 -070070config USES_MICROCODE_HEADER_FILES
71 def_bool n
73 help
74 This is selected by a board or chipset to set the default for the
75 microcode source choice to a list of external microcode headers
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -050077choice
Stefan Reinauer9c29cfa2013-02-27 20:24:11 +010078 prompt "Include CPU microcode in CBFS" if ARCH_X86
Martin Roth4c502692015-11-05 08:03:45 -070079 default CPU_MICROCODE_CBFS_EXTERNAL_HEADER if USES_MICROCODE_HEADER_FILES
Paul Menzelbdaeea52015-03-07 09:15:02 +010080 default CPU_MICROCODE_CBFS_GENERATE if SUPPORT_CPU_UCODE_IN_CBFS && USE_BLOBS
Alexandru Gagniuc66e0c4c2013-12-04 22:21:15 -060081 default CPU_MICROCODE_CBFS_NONE if !SUPPORT_CPU_UCODE_IN_CBFS
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -050082
84 bool "Generate from tree"
85 help
86 Select this option if you want microcode updates to be assembled when
87 building coreboot and included in the final image as a separate CBFS
88 file. Microcode will not be hard-coded into ramstage.
Stefan Tauner0ce2b432013-04-01 13:45:44 +020090 The microcode file may be removed from the ROM image at a later
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -050091 time with cbfstool, if desired.
93 If unsure, select this option.
Martin Roth4c502692015-11-05 08:03:45 -070095config CPU_MICROCODE_CBFS_EXTERNAL_HEADER
96 bool "Include external microcode header files"
97 help
98 Select this option if you want to include external c header files
99 containing the CPU microcode. This will be included as a separate
100 file in CBFS.
102 A word of caution: only select this option if you are sure the
103 microcode that you have is newer than the microcode shipping with
104 coreboot.
106 The microcode file may be removed from the ROM image at a later
107 time with cbfstool, if desired.
109 If unsure, select "Generate from tree"
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -0500111config CPU_MICROCODE_CBFS_NONE
112 bool "Do not include microcode updates"
113 help
114 Select this option if you do not want CPU microcode included in CBFS.
115 Note that for some CPUs, the microcode is hard-coded into the source
116 tree and is not loaded from CBFS. In this case, microcode will still
117 be updated. There is a push to move all microcode to CBFS, but this
118 change is not implemented for all CPUs.
120 This option currently applies to:
121 - Intel SandyBridge/IvyBridge
122 - VIA Nano
124 Microcode may be added to the ROM image at a later time with cbfstool,
125 if desired.
127 If unsure, select "Generate from tree"
129 The GOOD:
130 Microcode updates intend to solve issues that have been discovered
131 after CPU production. The expected effect is that systems work as
132 intended with the updated microcode, but we have also seen cases where
133 issues were solved by not applying microcode updates.
135 The BAD:
136 Note that some operating system include these same microcode patches,
137 so you may need to also disable microcode updates in your operating
138 system for this option to have an effect.
140 The UGLY:
141 A word of CAUTION: some CPUs depend on microcode updates to function
142 correctly. Not updating the microcode may leave the CPU operating at
143 less than optimal performance, or may cause outright hangups.
144 There are CPUs where coreboot cannot properly initialize the CPU
145 without microcode updates
146 For example, if running with the factory microcode, some Intel
147 SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs
148 will hang when changing the frequency.
150 Make sure you have a way of flashing the ROM externally before
151 selecting this option.
Jens Rottmann686dc0d2013-02-18 17:26:01 +0100154
Timothy Pearson24e6d042015-10-08 16:58:58 -0500155config CPU_MICROCODE_MULTIPLE_FILES
156 bool
157 default n
159 help
160 Select this option to install separate microcode container files into
161 CBFS instead of using the traditional monolithic microcode file format.
Martin Roth4c502692015-11-05 08:03:45 -0700162
164 string "List of space separated microcode header files with the path"
166 help
167 A list of one or more microcode header files with path from the
168 coreboot directory. These should be separated by spaces.