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review.coreboot.org / coreboot / ae593879f5a589df7c88d0bbce966657891e93c5 / . / src / northbridge / intel / pineview / acpi / hostbridge.asl
blob: 4de9302802de153bea6a36f09539ebcbd249401a [file] [log] [blame]
Damien Zammitf7060f12015-11-14 00:59:21 +1100[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
Damien Zammitf7060f12015-11-14 00:59:21 +1100[diff] [blame]4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; version 2 of
8 * the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <arch/ioapic.h>
17
18Name(_HID,EISAID("PNP0A08")) // PCIe
19Name(_CID,EISAID("PNP0A03")) // PCI
20
Damien Zammitf7060f12015-11-14 00:59:21 +1100[diff] [blame]21Name(_BBN, 0)
22
23Device (MCHC)
24{
25 Name(_ADR, 0x00000000) /* 0:0.0 */
26
27 OperationRegion(MCHP, PCI_Config, 0x00, 0x100)
28 Field (MCHP, DWordAcc, NoLock, Preserve)
29 {
30 Offset (0x40), /* EPBAR */
31 EPEN, 1, /* Enable */
32 , 11,
33 EPBR, 24, /* EPBAR */
34
35 Offset (0x48), /* MCHBAR */
36 MHEN, 1, /* Enable */
37 , 13,
38 MHBR, 22, /* MCHBAR */
39
40 Offset (0x60), /* PCIec BAR */
41 PXEN, 1, /* Enable */
42 PXSZ, 2, /* BAR size */
43 , 23,
44 PXBR, 10, /* PCIec BAR */
45
46 Offset (0x68), /* DMIBAR */
47 DMEN, 1, /* Enable */
48 , 11, /*
49 DMBR, 20, /* DMIBAR */
50
51 // ...
52
53 Offset (0x90), /* PAM0 */
54 , 4,
55 PM0H, 2,
56 , 2,
57 Offset (0x91), /* PAM1 */
58 PM1L, 2,
59 , 2,
60 PM1H, 2,
61 , 2,
62 Offset (0x92), /* PAM2 */
63 PM2L, 2,
64 , 2,
65 PM2H, 2,
66 , 2,
67 Offset (0x93), /* PAM3 */
68 PM3L, 2,
69 , 2,
70 PM3H, 2,
71 , 2,
72 Offset (0x94), /* PAM4 */
73 PM4L, 2,
74 , 2,
75 PM4H, 2,
76 , 2,
77 Offset (0x95), /* PAM5 */
78 PM5L, 2,
79 , 2,
80 PM5H, 2,
81 , 2,
82 Offset (0x96), /* PAM6 */
83 PM6L, 2,
84 , 2,
85 PM6H, 2,
86 , 2,
87
88 Offset (0xa0), /* Top of Memory */
89 TOM, 8,
90
91 Offset (0xb0), /* Top of Low Used Memory */
92 , 4,
93 TLUD, 12,
94
95 }
96
97}
98
99
100/* Current Resource Settings */
101Name (MCRS, ResourceTemplate()
102{
103 /* Bus Numbers */
104 WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
105 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00)
106
107 /* IO Region 0 */
108 DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
109 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00)
110
111 /* PCI Config Space */
112 Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
113
114 /* IO Region 1 */
115 DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
116 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01)
117
118 /* VGA memory (0xa0000-0xbffff) */
119 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
120 Cacheable, ReadWrite,
121 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
122 0x00020000,,, ASEG)
123
124 /* OPROM reserved (0xc0000-0xc3fff) */
125 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
126 Cacheable, ReadWrite,
127 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
128 0x00004000,,, OPR0)
129
130 /* OPROM reserved (0xc4000-0xc7fff) */
131 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
132 Cacheable, ReadWrite,
133 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
134 0x00004000,,, OPR1)
135
136 /* OPROM reserved (0xc8000-0xcbfff) */
137 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
138 Cacheable, ReadWrite,
139 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
140 0x00004000,,, OPR2)
141
142 /* OPROM reserved (0xcc000-0xcffff) */
143 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
144 Cacheable, ReadWrite,
145 0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
146 0x00004000,,, OPR3)
147
148 /* OPROM reserved (0xd0000-0xd3fff) */
149 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
150 Cacheable, ReadWrite,
151 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
152 0x00004000,,, OPR4)
153
154 /* OPROM reserved (0xd4000-0xd7fff) */
155 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
156 Cacheable, ReadWrite,
157 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
158 0x00004000,,, OPR5)
159
160 /* OPROM reserved (0xd8000-0xdbfff) */
161 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
162 Cacheable, ReadWrite,
163 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
164 0x00004000,,, OPR6)
165
166 /* OPROM reserved (0xdc000-0xdffff) */
167 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
168 Cacheable, ReadWrite,
169 0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
170 0x00004000,,, OPR7)
171
172 /* BIOS Extension (0xe0000-0xe3fff) */
173 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
174 Cacheable, ReadWrite,
175 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
176 0x00004000,,, ESG0)
177
178 /* BIOS Extension (0xe4000-0xe7fff) */
179 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
180 Cacheable, ReadWrite,
181 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
182 0x00004000,,, ESG1)
183
184 /* BIOS Extension (0xe8000-0xebfff) */
185 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
186 Cacheable, ReadWrite,
187 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
188 0x00004000,,, ESG2)
189
190 /* BIOS Extension (0xec000-0xeffff) */
191 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
192 Cacheable, ReadWrite,
193 0x00000000, 0x000ec000, 0x000effff, 0x00000000,
194 0x00004000,,, ESG3)
195
196 /* System BIOS (0xf0000-0xfffff) */
197 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
198 Cacheable, ReadWrite,
199 0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
200 0x00010000,,, FSEG)
201
202 /* PCI Memory Region (Top of memory-0xfebfffff) */
203 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
204 Cacheable, ReadWrite,
205 0x00000000, 0x00000000, 0xfebfffff, 0x00000000,
206 IO_APIC_ADDR,,, PM01)
207
208 /* TPM Area (0xfed40000-0xfed44fff) */
209 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
210 Cacheable, ReadWrite,
211 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
212 0x00005000,,, TPMR)
213})
214
215Method (_CRS, 0, Serialized)
216{
217 /* Find PCI resource area in MCRS */
218 CreateDwordField(MCRS, ^PM01._MIN, PMIN)
219 CreateDwordField(MCRS, ^PM01._MAX, PMAX)
220 CreateDwordField(MCRS, ^PM01._LEN, PLEN)
221
222 /* Fix up PCI memory region:
223 * Enter actual TOLUD. The TOLUD register contains bits 27-31 of
224 * the top of memory address.
225 */
226 ShiftLeft (^MCHC.TLUD, 27, PMIN)
227 Add(Subtract(PMAX, PMIN), 1, PLEN)
228
229 Return (MCRS)
230}