Kyösti Mälkki | 191d221 | 2014-06-15 12:06:12 +0300 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Kyösti Mälkki | 191d221 | 2014-06-15 12:06:12 +0300 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; version 2 of the License. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
Kyösti Mälkki | 191d221 | 2014-06-15 12:06:12 +0300 | [diff] [blame] | 13 | */ |
| 14 | |
| 15 | #define __SIMPLE_DEVICE__ |
| 16 | |
Kyösti Mälkki | a963acd | 2019-08-16 20:34:25 +0300 | [diff] [blame] | 17 | #include <arch/romstage.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 18 | #include <device/pci_ops.h> |
Kyösti Mälkki | 191d221 | 2014-06-15 12:06:12 +0300 | [diff] [blame] | 19 | #include <cbmem.h> |
Kyösti Mälkki | 2c3fd49 | 2016-07-22 22:52:14 +0300 | [diff] [blame] | 20 | #include <cpu/x86/mtrr.h> |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 21 | #include <cpu/x86/smm.h> |
Kyösti Mälkki | 2c3fd49 | 2016-07-22 22:52:14 +0300 | [diff] [blame] | 22 | #include <program_loading.h> |
Kyösti Mälkki | f091f4d | 2019-08-14 03:49:21 +0300 | [diff] [blame] | 23 | #include <cpu/intel/smm_reloc.h> |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 24 | #include "ironlake.h" |
Kyösti Mälkki | 191d221 | 2014-06-15 12:06:12 +0300 | [diff] [blame] | 25 | |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 26 | static uintptr_t smm_region_start(void) |
Kyösti Mälkki | 191d221 | 2014-06-15 12:06:12 +0300 | [diff] [blame] | 27 | { |
| 28 | /* Base of TSEG is top of usable DRAM */ |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 29 | uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); |
| 30 | return tom; |
| 31 | } |
| 32 | |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 33 | static uintptr_t northbridge_get_tseg_base(void) |
Arthur Heymans | 97c7c6b | 2018-05-15 16:45:21 +0200 | [diff] [blame] | 34 | { |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 35 | return smm_region_start(); |
Arthur Heymans | 97c7c6b | 2018-05-15 16:45:21 +0200 | [diff] [blame] | 36 | } |
| 37 | |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 38 | static size_t northbridge_get_tseg_size(void) |
Kyösti Mälkki | f6c2068 | 2019-08-02 06:14:50 +0300 | [diff] [blame] | 39 | { |
| 40 | return CONFIG_SMM_TSEG_SIZE; |
| 41 | } |
| 42 | |
Arthur Heymans | 340e4b8 | 2019-10-23 17:25:58 +0200 | [diff] [blame] | 43 | void *cbmem_top_chipset(void) |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 44 | { |
| 45 | return (void *) smm_region_start(); |
Kyösti Mälkki | 191d221 | 2014-06-15 12:06:12 +0300 | [diff] [blame] | 46 | } |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 47 | |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 48 | void smm_region(uintptr_t *start, size_t *size) |
Kyösti Mälkki | f6c2068 | 2019-08-02 06:14:50 +0300 | [diff] [blame] | 49 | { |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 50 | *start = northbridge_get_tseg_base(); |
| 51 | *size = northbridge_get_tseg_size(); |
Kyösti Mälkki | f6c2068 | 2019-08-02 06:14:50 +0300 | [diff] [blame] | 52 | } |
| 53 | |
Kyösti Mälkki | 5bc641a | 2019-08-09 09:37:49 +0300 | [diff] [blame] | 54 | void fill_postcar_frame(struct postcar_frame *pcf) |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 55 | { |
Kyösti Mälkki | 2c3fd49 | 2016-07-22 22:52:14 +0300 | [diff] [blame] | 56 | uintptr_t top_of_ram; |
| 57 | |
Kyösti Mälkki | 2c3fd49 | 2016-07-22 22:52:14 +0300 | [diff] [blame] | 58 | /* Cache at least 8 MiB below the top of ram, and at most 8 MiB |
| 59 | * above top of the ram. This satisfies MTRR alignment requirement |
| 60 | * with different TSEG size configurations. |
| 61 | */ |
| 62 | top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); |
Kyösti Mälkki | 5bc641a | 2019-08-09 09:37:49 +0300 | [diff] [blame] | 63 | postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); |
| 64 | postcar_frame_add_mtrr(pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK); |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 65 | } |