Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or |
| 6 | * modify it under the terms of the GNU General Public License as |
| 7 | * published by the Free Software Foundation; version 2 of |
| 8 | * the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <stdint.h> |
| 17 | #include <cf9_reset.h> |
| 18 | #include <cpu/x86/lapic.h> |
| 19 | #include <console/console.h> |
| 20 | #include <arch/romstage.h> |
| 21 | #include <northbridge/intel/i945/i945.h> |
| 22 | #include <northbridge/intel/i945/raminit.h> |
| 23 | #include <southbridge/intel/i82801gx/i82801gx.h> |
| 24 | #include <southbridge/intel/common/pmclib.h> |
| 25 | |
| 26 | __weak void mainboard_lpc_decode(void) |
| 27 | { |
| 28 | } |
| 29 | |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 30 | __weak void mainboard_pre_raminit_config(int s3_resume) |
| 31 | { |
| 32 | } |
| 33 | |
| 34 | __weak void mainboard_get_spd_map(u8 spd_map[4]) |
| 35 | { |
| 36 | spd_map[0] = 0x50; |
| 37 | spd_map[1] = 0x51; |
| 38 | spd_map[2] = 0x52; |
| 39 | spd_map[3] = 0x53; |
| 40 | } |
| 41 | |
| 42 | void mainboard_romstage_entry(void) |
| 43 | { |
| 44 | int s3resume = 0; |
| 45 | u8 spd_map[4] = {}; |
| 46 | |
| 47 | enable_lapic(); |
| 48 | |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 49 | mainboard_lpc_decode(); |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 50 | |
| 51 | if (MCHBAR16(SSKPD) == 0xCAFE) { |
| 52 | system_reset(); |
| 53 | } |
| 54 | |
| 55 | /* Perform some early chipset initialization required |
| 56 | * before RAM initialization can work |
| 57 | */ |
| 58 | i82801gx_early_init(); |
| 59 | i945_early_initialization(); |
| 60 | |
| 61 | s3resume = southbridge_detect_s3_resume(); |
| 62 | |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 63 | mainboard_pre_raminit_config(s3resume); |
| 64 | |
| 65 | if (CONFIG(DEBUG_RAM_SETUP)) |
| 66 | dump_spd_registers(); |
| 67 | |
| 68 | mainboard_get_spd_map(spd_map); |
| 69 | |
Paul Menzel | e0cd2eb | 2020-01-19 00:07:05 +0100 | [diff] [blame] | 70 | sdram_initialize(s3resume ? BOOT_PATH_RESUME : BOOT_PATH_NORMAL, spd_map); |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 71 | |
| 72 | /* This should probably go away. Until now it is required |
| 73 | * and mainboard specific |
| 74 | */ |
| 75 | mainboard_late_rcba_config(); |
| 76 | |
| 77 | /* Chipset Errata! */ |
Elyes HAOUAS | 8273e13 | 2020-03-10 22:17:12 +0100 | [diff] [blame] | 78 | if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) |
| 79 | fixup_i945gm_errata(); |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 80 | |
| 81 | /* Initialize the internal PCIe links before we go into stage2 */ |
| 82 | i945_late_initialization(s3resume); |
| 83 | } |