blob: b7823ebf590d2dc4ba340325d085bb233e09d636 [file] [log] [blame]
Vladimir Serbinenko888d5592013-11-13 17:53:38 +01001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2008-2009 coresystems GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
9 * the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Vladimir Serbinenko888d5592013-11-13 17:53:38 +010015 */
16
17#include <arch/io.h>
18#include <console/console.h>
19#include <device/pci_ids.h>
20#include <device/pci_def.h>
Arthur Heymans16fe7902017-04-12 17:01:31 +020021#include <southbridge/intel/common/smbus.h>
Vladimir Serbinenko888d5592013-11-13 17:53:38 +010022#include "pch.h"
Vladimir Serbinenko888d5592013-11-13 17:53:38 +010023
24void enable_smbus(void)
25{
Antonello Dettori040117a2016-09-02 09:15:33 +020026 pci_devfn_t dev;
Vladimir Serbinenko888d5592013-11-13 17:53:38 +010027
28 /* Set the SMBus device statically. */
29 dev = PCI_DEV(0x0, 0x1f, 0x3);
30
31 /* Check to make sure we've got the right device. */
32 if (pci_read_config16(dev, 0x0) != 0x8086) {
33 die("SMBus controller not found!");
34 }
35
36 /* Set SMBus I/O base. */
37 pci_write_config32(dev, SMB_BASE,
38 SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
39
40 /* Set SMBus enable. */
41 pci_write_config8(dev, HOSTC, HST_EN);
42
43 /* Set SMBus I/O space enable. */
44 pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
45
46 /* Disable interrupt generation. */
47 outb(0, SMBUS_IO_BASE + SMBHSTCTL);
48
49 /* Clear any lingering errors, so transactions can run. */
50 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
Stefan Reinauer5ab52dd2015-01-05 13:01:01 -080051 printk(BIOS_DEBUG, "SMBus controller enabled.\n");
Vladimir Serbinenko888d5592013-11-13 17:53:38 +010052}
53
54int smbus_read_byte(unsigned device, unsigned address)
55{
56 return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
57}
58
59int smbus_write_byte(unsigned device, unsigned address, u8 data)
60{
61 return do_smbus_write_byte(SMBUS_IO_BASE, device, address, data);
62}
63
64int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf)
65{
66 return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf);
67}
68
69int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf)
70{
71 return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf);
72}