blob: a036858d0427c0d6a9e5de03b7d2fd1630ad3daf [file] [log] [blame]
Stefan Reinauer8e073822012-04-04 00:07:22 +02001/*
2 * This file is part of the coreboot project.
3 *
Alexandru Gagniucecf2eb42015-09-28 21:39:12 -07004 * Copyright (C) 2014 Vladimir Serbinenko
Stefan Reinauer8e073822012-04-04 00:07:22 +02005 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
9 * the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Stefan Reinauer8e073822012-04-04 00:07:22 +020015 */
16
17#include <arch/io.h>
Stefan Reinauer8e073822012-04-04 00:07:22 +020018#include <console/console.h>
19#include <device/pci_ids.h>
20#include <device/pci_def.h>
Alexandru Gagniucecf2eb42015-09-28 21:39:12 -070021#include "northbridge/intel/sandybridge/sandybridge.h" /* For DEFAULT_RCBABASE. */
Stefan Reinauer8e073822012-04-04 00:07:22 +020022#include "pch.h"
23
Alexandru Gagniucecf2eb42015-09-28 21:39:12 -070024void
25early_usb_init (const struct southbridge_usb_port *portmap)
Stefan Reinauer8e073822012-04-04 00:07:22 +020026{
Alexandru Gagniucecf2eb42015-09-28 21:39:12 -070027 u32 reg32;
28 const u32 rcba_dump[8] = {
29 /* 3560 */ 0x024c8001, 0x000024a3, 0x00040002, 0x01000050,
30 /* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630,
31 };
Vagiz Trakhanov216ad212017-09-28 14:54:52 +000032 const u32 currents[] = { 0x20000153, 0x20000f57, 0x2000055b, 0x20000f51,
33 0x2000094a, 0x2000035f, 0x20000f53, 0x20000357,
34 0x20000353 };
Alexandru Gagniucecf2eb42015-09-28 21:39:12 -070035 int i;
36 /* Activate PMBAR. */
37 pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
38 pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0);
39 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
Stefan Reinauer8e073822012-04-04 00:07:22 +020040
Alexandru Gagniucecf2eb42015-09-28 21:39:12 -070041 /* Unlock registers. */
Patrick Rudolph87b5ff02017-05-28 13:57:04 +020042 outw(inw(DEFAULT_PMBASE | UPRWC) | UPRWC_WR_EN,
43 DEFAULT_PMBASE | UPRWC);
44
Alexandru Gagniucecf2eb42015-09-28 21:39:12 -070045 for (i = 0; i < 14; i++)
46 write32 (DEFAULT_RCBABASE + (0x3500 + 4 * i),
47 currents[portmap[i].current]);
48 for (i = 0; i < 10; i++)
49 write32 (DEFAULT_RCBABASE + (0x3538 + 4 * i), 0);
Stefan Reinauer8e073822012-04-04 00:07:22 +020050
Alexandru Gagniucecf2eb42015-09-28 21:39:12 -070051 for (i = 0; i < 8; i++)
52 write32 (DEFAULT_RCBABASE + (0x3560 + 4 * i), rcba_dump[i]);
53 for (i = 0; i < 8; i++)
54 write32 (DEFAULT_RCBABASE + (0x3580 + 4 * i), 0);
55 reg32 = 0;
56 for (i = 0; i < 14; i++)
57 if (!portmap[i].enabled)
58 reg32 |= (1 << i);
59 write32 (DEFAULT_RCBABASE + USBPDO, reg32);
60 reg32 = 0;
61 for (i = 0; i < 8; i++)
62 if (portmap[i].enabled && portmap[i].oc_pin >= 0)
63 reg32 |= (1 << (i + 8 * portmap[i].oc_pin));
64 write32 (DEFAULT_RCBABASE + USBOCM1, reg32);
65 reg32 = 0;
66 for (i = 8; i < 14; i++)
67 if (portmap[i].enabled && portmap[i].oc_pin >= 4)
68 reg32 |= (1 << (i - 8 + 8 * (portmap[i].oc_pin - 4)));
69 write32 (DEFAULT_RCBABASE + USBOCM2, reg32);
70 for (i = 0; i < 22; i++)
71 write32 (DEFAULT_RCBABASE + (0x35a8 + 4 * i), 0);
72
Kyösti Mälkkid45114f2013-07-26 08:53:59 +030073 pci_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000);
Alexandru Gagniucecf2eb42015-09-28 21:39:12 -070074
75 /* Relock registers. */
Patrick Rudolph87b5ff02017-05-28 13:57:04 +020076 outw(0, DEFAULT_PMBASE | UPRWC);
Stefan Reinauer8e073822012-04-04 00:07:22 +020077}