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Stefan Reinauer8e073822012-04-04 00:07:22 +02001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
9 * the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Stefan Reinauer8e073822012-04-04 00:07:22 +020015 */
16
Stefan Reinauer8e073822012-04-04 00:07:22 +020017#include <arch/io.h>
Stefan Reinauer8e073822012-04-04 00:07:22 +020018#include <console/console.h>
19#include <delay.h>
20#include <device/pci_ids.h>
Nicola Corna14604da2018-05-15 17:15:03 +020021#include <device/pci_def.h>
Patrick Georgi546953c2014-11-29 10:38:17 +010022#include <halt.h>
Stefan Reinauer8e073822012-04-04 00:07:22 +020023#include <string.h>
Nathaniel Roach52f08712017-09-09 19:58:08 +080024#include <timestamp.h>
Stefan Reinauer8e073822012-04-04 00:07:22 +020025#include "me.h"
26#include "pch.h"
27
28static const char *me_ack_values[] = {
29 [ME_HFS_ACK_NO_DID] = "No DID Ack received",
30 [ME_HFS_ACK_RESET] = "Non-power cycle reset",
31 [ME_HFS_ACK_PWR_CYCLE] = "Power cycle reset",
32 [ME_HFS_ACK_S3] = "Go to S3",
33 [ME_HFS_ACK_S4] = "Go to S4",
34 [ME_HFS_ACK_S5] = "Go to S5",
35 [ME_HFS_ACK_GBL_RESET] = "Global Reset",
36 [ME_HFS_ACK_CONTINUE] = "Continue to boot"
37};
38
39static inline void pci_read_dword_ptr(void *ptr, int offset)
40{
41 u32 dword = pci_read_config32(PCH_ME_DEV, offset);
42 memcpy(ptr, &dword, sizeof(dword));
43}
44
Stefan Reinauer8e073822012-04-04 00:07:22 +020045void intel_early_me_status(void)
46{
47 struct me_hfs hfs;
48 struct me_gmes gmes;
Nicola Corna14604da2018-05-15 17:15:03 +020049 u32 id = pci_read_config32(PCH_ME_DEV, PCI_VENDOR_ID);
Stefan Reinauer8e073822012-04-04 00:07:22 +020050
Nicola Corna14604da2018-05-15 17:15:03 +020051 if ((id == 0xffffffff) || (id == 0x00000000) ||
52 (id == 0x0000ffff) || (id == 0xffff0000)) {
53 printk(BIOS_DEBUG, "Missing Intel ME PCI device.\n");
54 } else {
55 pci_read_dword_ptr(&hfs, PCI_ME_HFS);
56 pci_read_dword_ptr(&gmes, PCI_ME_GMES);
Stefan Reinauer8e073822012-04-04 00:07:22 +020057
Nicola Corna14604da2018-05-15 17:15:03 +020058 intel_me_status(&hfs, &gmes);
59 }
Stefan Reinauer8e073822012-04-04 00:07:22 +020060}
61
62int intel_early_me_init(void)
63{
64 int count;
65 struct me_uma uma;
66 struct me_hfs hfs;
67
68 printk(BIOS_INFO, "Intel ME early init\n");
69
70 /* Wait for ME UMA SIZE VALID bit to be set */
71 for (count = ME_RETRY; count > 0; --count) {
72 pci_read_dword_ptr(&uma, PCI_ME_UMA);
73 if (uma.valid)
74 break;
75 udelay(ME_DELAY);
76 }
77 if (!count) {
78 printk(BIOS_ERR, "ERROR: ME is not ready!\n");
79 return -1;
80 }
81
82 /* Check for valid firmware */
83 pci_read_dword_ptr(&hfs, PCI_ME_HFS);
84 if (hfs.fpt_bad) {
85 printk(BIOS_WARNING, "WARNING: ME has bad firmware\n");
86 return -1;
87 }
88
89 printk(BIOS_INFO, "Intel ME firmware is ready\n");
90 return 0;
91}
92
93int intel_early_me_uma_size(void)
94{
95 struct me_uma uma;
96
97 pci_read_dword_ptr(&uma, PCI_ME_UMA);
98 if (uma.valid) {
99 printk(BIOS_DEBUG, "ME: Requested %uMB UMA\n", uma.size);
100 return uma.size;
101 }
102
103 printk(BIOS_DEBUG, "ME: Invalid UMA size\n");
104 return 0;
105}
106
107static inline void set_global_reset(int enable)
108{
109 u32 etr3 = pci_read_config32(PCH_LPC_DEV, ETR3);
110
111 /* Clear CF9 Without Resume Well Reset Enable */
112 etr3 &= ~ETR3_CWORWRE;
113
114 /* CF9GR indicates a Global Reset */
115 if (enable)
116 etr3 |= ETR3_CF9GR;
117 else
118 etr3 &= ~ETR3_CF9GR;
119
120 pci_write_config32(PCH_LPC_DEV, ETR3, etr3);
121}
122
123int intel_early_me_init_done(u8 status)
124{
Alexandru Gagniucecf2eb42015-09-28 21:39:12 -0700125 u8 reset, errorcode, opmode;
126 u16 reg16;
Stefan Reinauer8e073822012-04-04 00:07:22 +0200127 u32 mebase_l, mebase_h;
Alexandru Gagniucecf2eb42015-09-28 21:39:12 -0700128 u32 millisec;
129 u32 hfs, me_fws2;
Stefan Reinauer8e073822012-04-04 00:07:22 +0200130 struct me_did did = {
131 .init_done = ME_INIT_DONE,
132 .status = status
133 };
Alexandru Gagniucecf2eb42015-09-28 21:39:12 -0700134 u32 meDID;
135
136 hfs = (pci_read_config32(PCI_DEV(0, 0x16, 0), PCI_ME_HFS) & 0xff000) >> 12;
137
138 opmode = (hfs & 0xf0) >> 4;
139 errorcode = hfs & 0xf;
140
141 if (opmode != ME_HFS_MODE_NORMAL) {
142 printk(BIOS_NOTICE, "ME: Wrong mode : %d\n", opmode);
143 //return 0;
144 }
145 if (errorcode) {
146 printk(BIOS_NOTICE, "ME: HFS error : %d\n", errorcode);
147 //return 0;
148 }
149
150 me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48);
151 printk(BIOS_NOTICE, "ME: FWS2: 0x%x\n", me_fws2);
152 printk(BIOS_NOTICE, "ME: Bist in progress: 0x%x\n", me_fws2 & 0x1);
153 printk(BIOS_NOTICE, "ME: ICC Status : 0x%x\n", (me_fws2 & 0x6) >> 1);
154 printk(BIOS_NOTICE, "ME: Invoke MEBx : 0x%x\n", (me_fws2 & 0x8) >> 3);
155 printk(BIOS_NOTICE, "ME: CPU replaced : 0x%x\n", (me_fws2 & 0x10) >> 4);
156 printk(BIOS_NOTICE, "ME: MBP ready : 0x%x\n", (me_fws2 & 0x20) >> 5);
157 printk(BIOS_NOTICE, "ME: MFS failure : 0x%x\n", (me_fws2 & 0x40) >> 6);
158 printk(BIOS_NOTICE, "ME: Warm reset req : 0x%x\n", (me_fws2 & 0x80) >> 7);
159 printk(BIOS_NOTICE, "ME: CPU repl valid : 0x%x\n", (me_fws2 & 0x100) >> 8);
160 printk(BIOS_NOTICE, "ME: (Reserved) : 0x%x\n", (me_fws2 & 0x600) >> 9);
161 printk(BIOS_NOTICE, "ME: FW update req : 0x%x\n", (me_fws2 & 0x800) >> 11);
162 printk(BIOS_NOTICE, "ME: (Reserved) : 0x%x\n", (me_fws2 & 0xf000) >> 12);
163 printk(BIOS_NOTICE, "ME: Current state : 0x%x\n", (me_fws2 & 0xff0000) >> 16);
164 printk(BIOS_NOTICE, "ME: Current PM event: 0x%x\n", (me_fws2 & 0xf000000) >> 24);
165 printk(BIOS_NOTICE, "ME: Progress code : 0x%x\n", (me_fws2 & 0xf0000000) >> 28);
166
Elyes HAOUAS1bcd7fc2016-07-28 21:20:04 +0200167 // Poll CPU replaced for 50ms
Alexandru Gagniucecf2eb42015-09-28 21:39:12 -0700168 millisec = 0;
169 while ((((me_fws2 & 0x100) >> 8) == 0) && millisec < 50) {
170 udelay(1000);
171 me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48);
172 millisec++;
173 }
174 if (millisec >= 50 || ((me_fws2 & 0x100) >> 8) == 0x0) {
175 printk(BIOS_NOTICE, "Waited long enough, or CPU was not replaced, continue...\n");
176 } else if ((me_fws2 & 0x100) == 0x100) {
177 if ((me_fws2 & 0x80) == 0x80) {
178 printk(BIOS_NOTICE, "CPU was replaced & warm reset required...\n");
Kyösti Mälkkid45114f2013-07-26 08:53:59 +0300179 reg16 = pci_read_config16(PCI_DEV(0, 31, 0), 0xa2) & ~0x80;
180 pci_write_config16(PCI_DEV(0, 31, 0), 0xa2, reg16);
Alexandru Gagniucecf2eb42015-09-28 21:39:12 -0700181 set_global_reset(0);
182 outb(0x6, 0xcf9);
183 halt();
184 }
185
186 if (((me_fws2 & 0x10) == 0x10) && (me_fws2 & 0x80) == 0x00) {
187 printk(BIOS_NOTICE, "Full training required\n");
188 }
189 }
190
191 printk(BIOS_NOTICE, "PASSED! Tell ME that DRAM is ready\n");
Stefan Reinauer8e073822012-04-04 00:07:22 +0200192
193 /* MEBASE from MESEG_BASE[35:20] */
194 mebase_l = pci_read_config32(PCI_CPU_DEVICE, PCI_CPU_MEBASE_L);
195 mebase_h = pci_read_config32(PCI_CPU_DEVICE, PCI_CPU_MEBASE_H) & 0xf;
196 did.uma_base = (mebase_l >> 20) | (mebase_h << 12);
197
Alexandru Gagniucecf2eb42015-09-28 21:39:12 -0700198 meDID = did.uma_base | (1 << 28);// | (1 << 23);
199 pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_ME_H_GS, meDID);
Stefan Reinauer8e073822012-04-04 00:07:22 +0200200
Stefan Reinauer8e073822012-04-04 00:07:22 +0200201 /* Must wait for ME acknowledgement */
Nathaniel Roachd7e0cb92017-09-09 19:59:07 +0800202 if (opmode == ME_HFS_MODE_DEBUG) {
203 printk(BIOS_NOTICE,
204 "ME: ME is reporting as disabled, "
205 "so not waiting for a response.\n");
206 } else {
207 timestamp_add_now(TS_ME_INFORM_DRAM_WAIT);
208 udelay(100);
209 millisec = 0;
210 do {
211 udelay(1000);
212 hfs = (pci_read_config32(
213 PCI_DEV(0, 0x16, 0), PCI_ME_HFS) & 0xfe000000)
214 >> 24;
215 millisec++;
216 } while ((((hfs & 0xf0) >> 4) != ME_HFS_BIOS_DRAM_ACK)
217 && (millisec <= 5000));
218 timestamp_add_now(TS_ME_INFORM_DRAM_DONE);
Stefan Reinauer8e073822012-04-04 00:07:22 +0200219 }
Nathaniel Roachd7e0cb92017-09-09 19:59:07 +0800220
Alexandru Gagniucecf2eb42015-09-28 21:39:12 -0700221
222 me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48);
223 printk(BIOS_NOTICE, "ME: FWS2: 0x%x\n", me_fws2);
224 printk(BIOS_NOTICE, "ME: Bist in progress: 0x%x\n", me_fws2 & 0x1);
225 printk(BIOS_NOTICE, "ME: ICC Status : 0x%x\n", (me_fws2 & 0x6) >> 1);
226 printk(BIOS_NOTICE, "ME: Invoke MEBx : 0x%x\n", (me_fws2 & 0x8) >> 3);
227 printk(BIOS_NOTICE, "ME: CPU replaced : 0x%x\n", (me_fws2 & 0x10) >> 4);
228 printk(BIOS_NOTICE, "ME: MBP ready : 0x%x\n", (me_fws2 & 0x20) >> 5);
229 printk(BIOS_NOTICE, "ME: MFS failure : 0x%x\n", (me_fws2 & 0x40) >> 6);
230 printk(BIOS_NOTICE, "ME: Warm reset req : 0x%x\n", (me_fws2 & 0x80) >> 7);
231 printk(BIOS_NOTICE, "ME: CPU repl valid : 0x%x\n", (me_fws2 & 0x100) >> 8);
232 printk(BIOS_NOTICE, "ME: (Reserved) : 0x%x\n", (me_fws2 & 0x600) >> 9);
233 printk(BIOS_NOTICE, "ME: FW update req : 0x%x\n", (me_fws2 & 0x800) >> 11);
234 printk(BIOS_NOTICE, "ME: (Reserved) : 0x%x\n", (me_fws2 & 0xf000) >> 12);
235 printk(BIOS_NOTICE, "ME: Current state : 0x%x\n", (me_fws2 & 0xff0000) >> 16);
236 printk(BIOS_NOTICE, "ME: Current PM event: 0x%x\n", (me_fws2 & 0xf000000) >> 24);
237 printk(BIOS_NOTICE, "ME: Progress code : 0x%x\n", (me_fws2 & 0xf0000000) >> 28);
238
Stefan Reinauer8e073822012-04-04 00:07:22 +0200239
240 /* Return the requested BIOS action */
241 printk(BIOS_NOTICE, "ME: Requested BIOS Action: %s\n",
Alexandru Gagniucecf2eb42015-09-28 21:39:12 -0700242 me_ack_values[(hfs & 0xe) >> 1]);
Stefan Reinauer8e073822012-04-04 00:07:22 +0200243
Alexandru Gagniucecf2eb42015-09-28 21:39:12 -0700244 reset = inb(0xcf9);
245 reset &= 0xf1;
246 switch ((hfs & 0xe) >> 1) {
247 case ME_HFS_ACK_NO_DID:
Stefan Reinauer8e073822012-04-04 00:07:22 +0200248 case ME_HFS_ACK_CONTINUE:
249 /* Continue to boot */
250 return 0;
251 case ME_HFS_ACK_RESET:
252 /* Non-power cycle reset */
253 set_global_reset(0);
Alexandru Gagniucecf2eb42015-09-28 21:39:12 -0700254 reset |= 0x06;
Stefan Reinauer8e073822012-04-04 00:07:22 +0200255 break;
256 case ME_HFS_ACK_PWR_CYCLE:
257 /* Power cycle reset */
258 set_global_reset(0);
Alexandru Gagniucecf2eb42015-09-28 21:39:12 -0700259 reset |= 0x0e;
Stefan Reinauer8e073822012-04-04 00:07:22 +0200260 break;
261 case ME_HFS_ACK_GBL_RESET:
262 /* Global reset */
263 set_global_reset(1);
Alexandru Gagniucecf2eb42015-09-28 21:39:12 -0700264 reset |= 0x0e;
Stefan Reinauer8e073822012-04-04 00:07:22 +0200265 break;
266 case ME_HFS_ACK_S3:
267 case ME_HFS_ACK_S4:
268 case ME_HFS_ACK_S5:
269 break;
270 }
271
272 /* Perform the requested reset */
273 if (reset) {
274 outb(reset, 0xcf9);
Patrick Georgi546953c2014-11-29 10:38:17 +0100275 halt();
Stefan Reinauer8e073822012-04-04 00:07:22 +0200276 }
277 return -1;
278}