blob: d7842cd6774c2c4009d83eb201e279ca0860c2a7 [file] [log] [blame]
Stefan Reinauer8e073822012-04-04 00:07:22 +02001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2009 coresystems GmbH
Duncan Lauriec3230362012-04-27 09:55:45 -07005 * Copyright (C) 2012 The Chromium OS Authors. All Rights Reserved.
Stefan Reinauer8e073822012-04-04 00:07:22 +02006 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of
10 * the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Stefan Reinauer8e073822012-04-04 00:07:22 +020016 */
17
Duncan Lauriec3230362012-04-27 09:55:45 -070018/* Intel 6/7 Series PCH PCIe support */
Stefan Reinauer8e073822012-04-04 00:07:22 +020019
20// PCI Express Ports
21
Duncan Lauriec3230362012-04-27 09:55:45 -070022Method (IRQM, 1, Serialized) {
Stefan Reinauer8e073822012-04-04 00:07:22 +020023
Duncan Lauriec3230362012-04-27 09:55:45 -070024 /* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */
25 Name (IQAA, Package() {
26 Package() { 0x0000ffff, 0, 0, 16 },
27 Package() { 0x0000ffff, 1, 0, 17 },
28 Package() { 0x0000ffff, 2, 0, 18 },
29 Package() { 0x0000ffff, 3, 0, 19 } })
30 Name (IQAP, Package() {
31 Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
32 Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
33 Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
34 Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } })
35
36 /* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */
37 Name (IQBA, Package() {
38 Package() { 0x0000ffff, 0, 0, 17 },
39 Package() { 0x0000ffff, 1, 0, 18 },
40 Package() { 0x0000ffff, 2, 0, 19 },
41 Package() { 0x0000ffff, 3, 0, 16 } })
42 Name (IQBP, Package() {
43 Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
44 Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
45 Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
46 Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 } })
47
48 /* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */
49 Name (IQCA, Package() {
50 Package() { 0x0000ffff, 0, 0, 18 },
51 Package() { 0x0000ffff, 1, 0, 19 },
52 Package() { 0x0000ffff, 2, 0, 16 },
53 Package() { 0x0000ffff, 3, 0, 17 } })
54 Name (IQCP, Package() {
55 Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
56 Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
57 Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
58 Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKB, 0 } })
59
60 /* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */
61 Name (IQDA, Package() {
62 Package() { 0x0000ffff, 0, 0, 19 },
63 Package() { 0x0000ffff, 1, 0, 16 },
64 Package() { 0x0000ffff, 2, 0, 17 },
65 Package() { 0x0000ffff, 3, 0, 18 } })
66 Name (IQDP, Package() {
67 Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
68 Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKA, 0 },
69 Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
70 Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKC, 0 } })
71
72 Switch (ToInteger (Arg0)) {
73 /* PCIe Root Port 1 and 5 */
74 Case (Package() { 1, 5 }) {
75 If (PICM) {
76 Return (IQAA)
77 } Else {
78 Return (IQAP)
79 }
Stefan Reinauer8e073822012-04-04 00:07:22 +020080 }
81
Duncan Lauriec3230362012-04-27 09:55:45 -070082 /* PCIe Root Port 2 and 6 */
83 Case (Package() { 2, 6 }) {
84 If (PICM) {
85 Return (IQBA)
86 } Else {
87 Return (IQBP)
88 }
89 }
90
91 /* PCIe Root Port 3 and 7 */
92 Case (Package() { 3, 7 }) {
93 If (PICM) {
94 Return (IQCA)
95 } Else {
96 Return (IQCP)
97 }
98 }
99
100 /* PCIe Root Port 4 and 8 */
101 Case (Package() { 4, 8 }) {
102 If (PICM) {
103 Return (IQDA)
104 } Else {
105 Return (IQDP)
106 }
107 }
108
109 Default {
110 If (PICM) {
111 Return (IQDA)
112 } Else {
113 Return (IQDP)
114 }
115 }
116 }
117}
118
119Device (RP01)
120{
121 Name (_ADR, 0x001c0000)
122
123 #include "pcie_port.asl"
124
125 Method (_PRT)
126 {
127 Return (IRQM (RPPN))
Stefan Reinauer8e073822012-04-04 00:07:22 +0200128 }
129}
130
131Device (RP02)
132{
Duncan Lauriec3230362012-04-27 09:55:45 -0700133 Name (_ADR, 0x001c0001)
134
135 #include "pcie_port.asl"
136
137 Method (_PRT)
Stefan Reinauer8e073822012-04-04 00:07:22 +0200138 {
Duncan Lauriec3230362012-04-27 09:55:45 -0700139 Return (IRQM (RPPN))
Stefan Reinauer8e073822012-04-04 00:07:22 +0200140 }
141}
142
143Device (RP03)
144{
Duncan Lauriec3230362012-04-27 09:55:45 -0700145 Name (_ADR, 0x001c0002)
146
147 #include "pcie_port.asl"
148
149 Method (_PRT)
Stefan Reinauer8e073822012-04-04 00:07:22 +0200150 {
Duncan Lauriec3230362012-04-27 09:55:45 -0700151 Return (IRQM (RPPN))
Stefan Reinauer8e073822012-04-04 00:07:22 +0200152 }
153}
154
155Device (RP04)
156{
Duncan Lauriec3230362012-04-27 09:55:45 -0700157 Name (_ADR, 0x001c0003)
158
159 #include "pcie_port.asl"
160
161 Method (_PRT)
Stefan Reinauer8e073822012-04-04 00:07:22 +0200162 {
Duncan Lauriec3230362012-04-27 09:55:45 -0700163 Return (IRQM (RPPN))
Stefan Reinauer8e073822012-04-04 00:07:22 +0200164 }
165}
166
167Device (RP05)
168{
Duncan Lauriec3230362012-04-27 09:55:45 -0700169 Name (_ADR, 0x001c0004)
170
171 #include "pcie_port.asl"
172
173 Method (_PRT)
Stefan Reinauer8e073822012-04-04 00:07:22 +0200174 {
Duncan Lauriec3230362012-04-27 09:55:45 -0700175 Return (IRQM (RPPN))
Stefan Reinauer8e073822012-04-04 00:07:22 +0200176 }
177}
178
179Device (RP06)
180{
Duncan Lauriec3230362012-04-27 09:55:45 -0700181 Name (_ADR, 0x001c0005)
182
183 #include "pcie_port.asl"
184
185 Method (_PRT)
Stefan Reinauer8e073822012-04-04 00:07:22 +0200186 {
Duncan Lauriec3230362012-04-27 09:55:45 -0700187 Return (IRQM (RPPN))
Stefan Reinauer8e073822012-04-04 00:07:22 +0200188 }
189}
190
191Device (RP07)
192{
Duncan Lauriec3230362012-04-27 09:55:45 -0700193 Name (_ADR, 0x001c0006)
194
195 #include "pcie_port.asl"
196
197 Method (_PRT)
Stefan Reinauer8e073822012-04-04 00:07:22 +0200198 {
Duncan Lauriec3230362012-04-27 09:55:45 -0700199 Return (IRQM (RPPN))
Stefan Reinauer8e073822012-04-04 00:07:22 +0200200 }
201}
202
203Device (RP08)
204{
Duncan Lauriec3230362012-04-27 09:55:45 -0700205 Name (_ADR, 0x001c0007)
206
207 #include "pcie_port.asl"
208
209 Method (_PRT)
Stefan Reinauer8e073822012-04-04 00:07:22 +0200210 {
Duncan Lauriec3230362012-04-27 09:55:45 -0700211 Return (IRQM (RPPN))
Stefan Reinauer8e073822012-04-04 00:07:22 +0200212 }
213}