Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <console/console.h> |
| 22 | #include <device/device.h> |
| 23 | #include <device/pci.h> |
| 24 | #include <device/pciexp.h> |
| 25 | #include <device/pci_ids.h> |
| 26 | #include "pch.h" |
| 27 | |
| 28 | static u16 pcie_port_link_width(int port) |
| 29 | { |
| 30 | u16 link_width; |
| 31 | |
| 32 | link_width = pci_read_config16( |
| 33 | dev_find_slot(0, PCI_DEVFN(0x1c, port)), 0x52); |
| 34 | link_width >>= 4; |
| 35 | link_width &= 0x3f; |
| 36 | return link_width; |
| 37 | } |
| 38 | |
| 39 | static void pch_pcie_pm_early(struct device *dev) |
| 40 | { |
| 41 | u16 link_width_p0, link_width_p4; |
| 42 | u8 slot_power_limit = 10; /* 10W for x1 */ |
| 43 | u32 reg32; |
| 44 | u8 reg8; |
| 45 | |
| 46 | link_width_p0 = pcie_port_link_width(0); |
| 47 | link_width_p4 = pcie_port_link_width(4); |
| 48 | |
| 49 | /* Enable dynamic clock gating where needed */ |
| 50 | reg8 = pci_read_config8(dev, 0xe1); |
| 51 | switch (PCI_FUNC(dev->path.pci.devfn)) { |
| 52 | case 0: /* Port 0 */ |
| 53 | if (link_width_p0 == 4) |
| 54 | slot_power_limit = 40; /* 40W for x4 */ |
| 55 | else if (link_width_p0 == 2) |
| 56 | slot_power_limit = 20; /* 20W for x2 */ |
| 57 | case 4: /* Port 4 */ |
| 58 | if (link_width_p4 == 4) |
| 59 | slot_power_limit = 40; /* 40W for x4 */ |
| 60 | else if (link_width_p4 == 2) |
| 61 | slot_power_limit = 20; /* 20W for x2 */ |
| 62 | reg8 |= 0x3f; |
| 63 | break; |
| 64 | case 1: /* Port 1 only if Port 0 is x1 */ |
| 65 | if (link_width_p0 == 1) |
| 66 | reg8 |= 0x3; |
| 67 | break; |
| 68 | case 2: /* Port 2 only if Port 0 is x1 or x2 */ |
| 69 | case 3: /* Port 3 only if Port 0 is x1 or x2 */ |
| 70 | if (link_width_p0 <= 2) |
| 71 | reg8 |= 0x3; |
| 72 | break; |
| 73 | case 5: /* Port 5 only if Port 4 is x1 */ |
| 74 | if (link_width_p4 == 1) |
| 75 | reg8 |= 0x3; |
| 76 | break; |
| 77 | case 6: /* Port 7 only if Port 4 is x1 or x2 */ |
| 78 | case 7: /* Port 7 only if Port 4 is x1 or x2 */ |
| 79 | if (link_width_p4 <= 2) |
| 80 | reg8 |= 0x3; |
| 81 | break; |
| 82 | } |
| 83 | pci_write_config8(dev, 0xe1, reg8); |
| 84 | |
| 85 | /* Set 0xE8[0] = 1 */ |
| 86 | reg32 = pci_read_config32(dev, 0xe8); |
| 87 | reg32 |= 1; |
| 88 | pci_write_config32(dev, 0xe8, reg32); |
| 89 | |
| 90 | /* Adjust Common Clock exit latency */ |
| 91 | reg32 = pci_read_config32(dev, 0xd8); |
| 92 | reg32 &= ~(1 << 17); |
| 93 | reg32 |= (1 << 16) | (1 << 15); |
| 94 | reg32 &= ~(1 << 31); /* Disable PME# SCI for native PME handling */ |
| 95 | pci_write_config32(dev, 0xd8, reg32); |
| 96 | |
| 97 | /* Adjust ASPM L1 exit latency */ |
| 98 | reg32 = pci_read_config32(dev, 0x4c); |
| 99 | reg32 &= ~((1 << 17) | (1 << 16) | (1 << 15)); |
| 100 | if (RCBA32(0x2320) & (1 << 16)) { |
| 101 | /* If RCBA+2320[15]=1 set ASPM L1 to 8-16us */ |
| 102 | reg32 |= (1 << 17); |
| 103 | } else { |
| 104 | /* Else set ASPM L1 to 2-4us */ |
| 105 | reg32 |= (1 << 16); |
| 106 | } |
| 107 | pci_write_config32(dev, 0x4c, reg32); |
| 108 | |
| 109 | /* Set slot power limit as configured above */ |
| 110 | reg32 = pci_read_config32(dev, 0x54); |
| 111 | reg32 &= ~((1 << 15) | (1 << 16)); /* 16:15 = Slot power scale */ |
| 112 | reg32 &= ~(0xff << 7); /* 14:7 = Slot power limit */ |
| 113 | reg32 |= (slot_power_limit << 7); |
| 114 | pci_write_config32(dev, 0x54, reg32); |
| 115 | } |
| 116 | |
| 117 | static void pch_pcie_pm_late(struct device *dev) |
| 118 | { |
| 119 | enum aspm_type apmc; |
| 120 | u32 reg32; |
| 121 | |
| 122 | /* Set 0x314 = 0x743a361b */ |
| 123 | pci_mmio_write_config32(dev, 0x314, 0x743a361b); |
| 124 | |
| 125 | /* Set 0x318[31:16] = 0x1414 */ |
| 126 | reg32 = pci_mmio_read_config32(dev, 0x318); |
| 127 | reg32 &= 0x0000ffff; |
| 128 | reg32 |= 0x14140000; |
| 129 | pci_mmio_write_config32(dev, 0x318, reg32); |
| 130 | |
| 131 | /* Set 0x324[5] = 1 */ |
| 132 | reg32 = pci_mmio_read_config32(dev, 0x324); |
| 133 | reg32 |= (1 << 5); |
| 134 | pci_mmio_write_config32(dev, 0x324, reg32); |
| 135 | |
| 136 | /* Set 0x330[7:0] = 0x40 */ |
| 137 | reg32 = pci_mmio_read_config32(dev, 0x330); |
| 138 | reg32 &= ~(0xff); |
| 139 | reg32 |= 0x40; |
| 140 | pci_mmio_write_config32(dev, 0x330, reg32); |
| 141 | |
| 142 | /* Set 0x33C[24:0] = 0x854c74 */ |
| 143 | reg32 = pci_mmio_read_config32(dev, 0x33c); |
| 144 | reg32 &= 0xff000000; |
| 145 | reg32 |= 0x00854c74; |
| 146 | pci_mmio_write_config32(dev, 0x33c, reg32); |
| 147 | |
| 148 | /* No IO-APIC, Disable EOI forwarding */ |
| 149 | reg32 = pci_read_config32(dev, 0xd4); |
| 150 | reg32 |= (1 << 1); |
| 151 | pci_write_config32(dev, 0xd4, reg32); |
| 152 | |
| 153 | /* Get configured ASPM state */ |
| 154 | apmc = pci_read_config32(dev, 0x50) & 3; |
| 155 | |
| 156 | /* If both L0s and L1 enabled then set root port 0xE8[1]=1 */ |
| 157 | if (apmc == PCIE_ASPM_BOTH) { |
| 158 | reg32 = pci_read_config32(dev, 0xe8); |
| 159 | reg32 |= (1 << 1); |
| 160 | pci_write_config32(dev, 0xe8, reg32); |
| 161 | } |
| 162 | } |
| 163 | |
| 164 | static void pci_init(struct device *dev) |
| 165 | { |
| 166 | u16 reg16; |
| 167 | u32 reg32; |
| 168 | |
| 169 | printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n"); |
| 170 | |
| 171 | /* Enable Bus Master */ |
| 172 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 173 | reg32 |= PCI_COMMAND_MASTER; |
| 174 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 175 | |
| 176 | /* Set Cache Line Size to 0x10 */ |
| 177 | // This has no effect but the OS might expect it |
| 178 | pci_write_config8(dev, 0x0c, 0x10); |
| 179 | |
| 180 | reg16 = pci_read_config16(dev, 0x3e); |
| 181 | reg16 &= ~(1 << 0); /* disable parity error response */ |
| 182 | // reg16 &= ~(1 << 1); /* disable SERR */ |
| 183 | reg16 |= (1 << 2); /* ISA enable */ |
| 184 | pci_write_config16(dev, 0x3e, reg16); |
| 185 | |
| 186 | #ifdef EVEN_MORE_DEBUG |
| 187 | reg32 = pci_read_config32(dev, 0x20); |
| 188 | printk(BIOS_SPEW, " MBL = 0x%08x\n", reg32); |
| 189 | reg32 = pci_read_config32(dev, 0x24); |
| 190 | printk(BIOS_SPEW, " PMBL = 0x%08x\n", reg32); |
| 191 | reg32 = pci_read_config32(dev, 0x28); |
| 192 | printk(BIOS_SPEW, " PMBU32 = 0x%08x\n", reg32); |
| 193 | reg32 = pci_read_config32(dev, 0x2c); |
| 194 | printk(BIOS_SPEW, " PMLU32 = 0x%08x\n", reg32); |
| 195 | #endif |
| 196 | |
| 197 | /* Clear errors in status registers */ |
| 198 | reg16 = pci_read_config16(dev, 0x06); |
| 199 | //reg16 |= 0xf900; |
| 200 | pci_write_config16(dev, 0x06, reg16); |
| 201 | |
| 202 | reg16 = pci_read_config16(dev, 0x1e); |
| 203 | //reg16 |= 0xf900; |
| 204 | pci_write_config16(dev, 0x1e, reg16); |
| 205 | |
| 206 | /* Power Management init after enumeration */ |
| 207 | pch_pcie_pm_late(dev); |
| 208 | } |
| 209 | |
| 210 | static void pch_pcie_enable(device_t dev) |
| 211 | { |
| 212 | /* Power Management init before enumeration */ |
| 213 | pch_pcie_pm_early(dev); |
| 214 | } |
| 215 | |
| 216 | static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 217 | { |
| 218 | /* NOTE: This is not the default position! */ |
| 219 | if (!vendor || !device) { |
| 220 | pci_write_config32(dev, 0x94, |
| 221 | pci_read_config32(dev, 0)); |
| 222 | } else { |
| 223 | pci_write_config32(dev, 0x94, |
| 224 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 225 | } |
| 226 | } |
| 227 | |
| 228 | static struct pci_operations pci_ops = { |
| 229 | .set_subsystem = pcie_set_subsystem, |
| 230 | }; |
| 231 | |
| 232 | static struct device_operations device_ops = { |
| 233 | .read_resources = pci_bus_read_resources, |
| 234 | .set_resources = pci_dev_set_resources, |
| 235 | .enable_resources = pci_bus_enable_resources, |
| 236 | .init = pci_init, |
| 237 | .enable = pch_pcie_enable, |
| 238 | .scan_bus = pciexp_scan_bridge, |
| 239 | .ops_pci = &pci_ops, |
| 240 | }; |
| 241 | |
| 242 | static const struct pci_driver pch_pcie_port1 __pci_driver = { |
| 243 | .ops = &device_ops, |
| 244 | .vendor = PCI_VENDOR_ID_INTEL, |
| 245 | .device = 0x1c10, /* D28:F0 */ |
| 246 | }; |
| 247 | |
| 248 | static const struct pci_driver pch_pcie_port1_a __pci_driver = { |
| 249 | .ops = &device_ops, |
| 250 | .vendor = PCI_VENDOR_ID_INTEL, |
| 251 | .device = 0x1e10, /* D28:F0 */ |
| 252 | }; |
| 253 | |
| 254 | static const struct pci_driver pch_pcie_port2 __pci_driver = { |
| 255 | .ops = &device_ops, |
| 256 | .vendor = PCI_VENDOR_ID_INTEL, |
| 257 | .device = 0x1c12, /* D28:F1 */ |
| 258 | }; |
| 259 | |
| 260 | static const struct pci_driver pch_pcie_port3 __pci_driver = { |
| 261 | .ops = &device_ops, |
| 262 | .vendor = PCI_VENDOR_ID_INTEL, |
| 263 | .device = 0x1c14, /* D28:F2 */ |
| 264 | }; |
| 265 | |
| 266 | static const struct pci_driver pch_pcie_port3_a __pci_driver = { |
| 267 | .ops = &device_ops, |
| 268 | .vendor = PCI_VENDOR_ID_INTEL, |
| 269 | .device = 0x1e14, /* D28:F2 */ |
| 270 | }; |
| 271 | |
| 272 | static const struct pci_driver pch_pcie_port4 __pci_driver = { |
| 273 | .ops = &device_ops, |
| 274 | .vendor = PCI_VENDOR_ID_INTEL, |
| 275 | .device = 0x1c16, /* D28:F3 */ |
| 276 | }; |
| 277 | |
| 278 | static const struct pci_driver pch_pcie_port4_a __pci_driver = { |
| 279 | .ops = &device_ops, |
| 280 | .vendor = PCI_VENDOR_ID_INTEL, |
| 281 | .device = 0x1e16, /* D28:F3 */ |
| 282 | }; |
| 283 | |
| 284 | static const struct pci_driver pch_pcie_port5 __pci_driver = { |
| 285 | .ops = &device_ops, |
| 286 | .vendor = PCI_VENDOR_ID_INTEL, |
| 287 | .device = 0x1c18, /* D28:F4 */ |
| 288 | }; |
| 289 | |
| 290 | static const struct pci_driver pch_pcie_port6 __pci_driver = { |
| 291 | .ops = &device_ops, |
| 292 | .vendor = PCI_VENDOR_ID_INTEL, |
| 293 | .device = 0x1c1a, /* D28:F5 */ |
| 294 | }; |
| 295 | |
| 296 | static const struct pci_driver pch_pcie_port7 __pci_driver = { |
| 297 | .ops = &device_ops, |
| 298 | .vendor = PCI_VENDOR_ID_INTEL, |
| 299 | .device = 0x1c1c, /* D28:F6 */ |
| 300 | }; |
| 301 | |
| 302 | static const struct pci_driver pch_pcie_port8 __pci_driver = { |
| 303 | .ops = &device_ops, |
| 304 | .vendor = PCI_VENDOR_ID_INTEL, |
| 305 | .device = 0x1c1e, /* D28:F7 */ |
| 306 | }; |