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Subrata Banikbaf6d6e2019-11-01 18:23:33 +05301/*
2 * This file is part of the coreboot project.
3 *
Wonkyu Kim1ab6f0c2020-01-28 22:06:37 -08004 * Copyright (C) 2019-2020 Intel Corp.
Subrata Banikbaf6d6e2019-11-01 18:23:33 +05305 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
Srinidhi N Kaushikd801b1f2019-12-27 13:28:01 -080016#include <assert.h>
17#include <console/console.h>
Subrata Banikbaf6d6e2019-11-01 18:23:33 +053018#include <fsp/util.h>
Srinidhi N Kaushikd801b1f2019-12-27 13:28:01 -080019#include <soc/gpio_soc_defs.h>
20#include <soc/iomap.h>
21#include <soc/pci_devs.h>
Subrata Banikbaf6d6e2019-11-01 18:23:33 +053022#include <soc/romstage.h>
Srinidhi N Kaushikd801b1f2019-12-27 13:28:01 -080023#include <soc/soc_chip.h>
24#include <string.h>
25
Srinidhi N Kaushikd801b1f2019-12-27 13:28:01 -080026static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
27 const struct soc_intel_tigerlake_config *config)
28{
29 unsigned int i;
30 uint32_t mask = 0;
Srinidhi N Kaushik18129f92020-03-10 15:40:42 -070031 const struct device *dev;
Srinidhi N Kaushikd801b1f2019-12-27 13:28:01 -080032
33 /* Set IGD stolen size to 60MB. */
34 m_cfg->IgdDvmt50PreAlloc = 0xFE;
35 m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
36 m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
37 m_cfg->SaGv = config->SaGv;
38 m_cfg->UserBd = BOARD_TYPE_ULT_ULX;
39 m_cfg->RMT = config->RMT;
40
41 for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
42 if (config->PcieRpEnable[i])
43 mask |= (1 << i);
44 }
45 m_cfg->PcieRpEnableMask = mask;
46
47 memcpy(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage,
48 sizeof(config->PcieClkSrcUsage));
49
50 for (i = 0; i < CONFIG_MAX_PCIE_CLOCKS; i++) {
51 if (config->PcieClkSrcUsage[i] == 0)
52 m_cfg->PcieClkSrcUsage[i] = 0xff;
53 }
54
Wonkyu Kim591b0ff2020-01-08 11:51:37 -080055 memcpy(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
56 sizeof(config->PcieClkSrcClkReq));
57
Srinidhi N Kaushikd801b1f2019-12-27 13:28:01 -080058 m_cfg->PrmrrSize = config->PrmrrSize;
59 m_cfg->EnableC6Dram = config->enable_c6dram;
60 /* Disable BIOS Guard */
61 m_cfg->BiosGuard = 0;
62
Wonkyu Kim591b0ff2020-01-08 11:51:37 -080063 /* UART Debug Log */
Srinidhi N Kaushikd801b1f2019-12-27 13:28:01 -080064 m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ?
Wonkyu Kim528ae9e2020-02-28 17:20:05 -080065 DEBUG_INTERFACE_UART|DEBUG_INTERFACE_TRACEHUB :
66 DEBUG_INTERFACE_SERIAL_IO|DEBUG_INTERFACE_TRACEHUB;
Srinidhi N Kaushikd801b1f2019-12-27 13:28:01 -080067 m_cfg->PcdIsaSerialUartBase = 0x0;
68 m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
69
70 /*
71 * Skip IGD initialization in FSP if device
72 * is disable in devicetree.cb.
73 */
Srinidhi N Kaushik18129f92020-03-10 15:40:42 -070074 dev = pcidev_path_on_root(SA_DEVFN_IGD);
Srinidhi N Kaushikd801b1f2019-12-27 13:28:01 -080075 if (!dev || !dev->enabled)
76 m_cfg->InternalGfx = 0;
77 else
78 m_cfg->InternalGfx = 0x1;
79
Wonkyu Kim9f2e3ad2020-01-23 00:06:07 -080080 /* DP port config */
81 m_cfg->DdiPortAConfig = config->DdiPortAConfig;
82 m_cfg->DdiPortBConfig = config->DdiPortBConfig;
83 m_cfg->DdiPortAHpd = config->DdiPortAHpd;
84 m_cfg->DdiPortBHpd = config->DdiPortBHpd;
85 m_cfg->DdiPortCHpd = config->DdiPortCHpd;
86 m_cfg->DdiPort1Hpd = config->DdiPort1Hpd;
87 m_cfg->DdiPort2Hpd = config->DdiPort2Hpd;
88 m_cfg->DdiPort3Hpd = config->DdiPort3Hpd;
89 m_cfg->DdiPort4Hpd = config->DdiPort4Hpd;
90 m_cfg->DdiPortADdc = config->DdiPortADdc;
91 m_cfg->DdiPortBDdc = config->DdiPortBDdc;
92 m_cfg->DdiPortCDdc = config->DdiPortCDdc;
93 m_cfg->DdiPort1Ddc = config->DdiPort1Ddc;
94 m_cfg->DdiPort2Ddc = config->DdiPort2Ddc;
95 m_cfg->DdiPort3Ddc = config->DdiPort3Ddc;
96 m_cfg->DdiPort4Ddc = config->DdiPort4Ddc;
97
Wonkyu Kimc332a472020-01-24 17:02:08 -080098 /* Image clock: disable all clocks for bypassing FSP pin mux */
99 memset(m_cfg->ImguClkOutEn, 0, sizeof(m_cfg->ImguClkOutEn));
100
Wonkyu Kim1ab6f0c2020-01-28 22:06:37 -0800101 /* Tcss */
102 m_cfg->TcssXhciEn = config->TcssXhciEn;
103 m_cfg->TcssXdciEn = config->TcssXdciEn;
104
Srinidhi N Kaushikd801b1f2019-12-27 13:28:01 -0800105 /* Enable Hyper Threading */
106 m_cfg->HyperThreading = 1;
107 /* Disable Lock PCU Thermal Management registers */
108 m_cfg->LockPTMregs = 0;
109 /* Channel Hash Mask:0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum) */
110 m_cfg->ChHashMask = 0x30CC;
111 /* Enable SMBus controller based on config */
112 m_cfg->SmbusEnable = config->SmbusEnable;
113 /* Set debug probe type */
Subrata Banik56626cf2020-02-27 19:39:22 +0530114 m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_TIGERLAKE_DEBUG_CONSENT;
Srinidhi N Kaushik2f2c7eb2020-01-02 16:11:27 -0800115
116 /* Audio: HDAUDIO_LINK_MODE I2S/SNDW */
Srinidhi N Kaushik18129f92020-03-10 15:40:42 -0700117 dev = pcidev_path_on_root(PCH_DEVFN_HDA);
118 if (!dev)
119 m_cfg->PchHdaEnable = 0;
120 else
121 m_cfg->PchHdaEnable = dev->enabled;
122
Srinidhi N Kaushik2f2c7eb2020-01-02 16:11:27 -0800123 m_cfg->PchHdaDspEnable = config->PchHdaDspEnable;
124 m_cfg->PchHdaAudioLinkHdaEnable = config->PchHdaAudioLinkHdaEnable;
125 memcpy(m_cfg->PchHdaAudioLinkDmicEnable, config->PchHdaAudioLinkDmicEnable,
126 sizeof(m_cfg->PchHdaAudioLinkDmicEnable));
127 memcpy(m_cfg->PchHdaAudioLinkSspEnable, config->PchHdaAudioLinkSspEnable,
128 sizeof(m_cfg->PchHdaAudioLinkSspEnable));
129 memcpy(m_cfg->PchHdaAudioLinkSndwEnable, config->PchHdaAudioLinkSndwEnable,
130 sizeof(m_cfg->PchHdaAudioLinkSndwEnable));
131 m_cfg->PchHdaIDispLinkTmode = config->PchHdaIDispLinkTmode;
132 m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency;
133 m_cfg->PchHdaIDispCodecDisconnect = config->PchHdaIDispCodecDisconnect;
John Zhao49111cd2020-01-03 11:01:23 -0800134
135 /* Vt-D config */
136 m_cfg->VtdDisable = 0;
137 m_cfg->VtdIgdEnable = 0x1;
138 m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS;
139 m_cfg->VtdIpuEnable = 0x1;
140 m_cfg->VtdBaseAddress[1] = IPUVT_BASE_ADDRESS;
141 m_cfg->VtdIopEnable = 0x1;
142 m_cfg->VtdBaseAddress[2] = VTVC0_BASE_ADDRESS;
143 m_cfg->VtdItbtEnable = 0x1;
144 m_cfg->VtdBaseAddress[3] = TBT0_BASE_ADDRESS;
145 m_cfg->VtdBaseAddress[4] = TBT1_BASE_ADDRESS;
146 m_cfg->VtdBaseAddress[5] = TBT2_BASE_ADDRESS;
147 m_cfg->VtdBaseAddress[6] = TBT3_BASE_ADDRESS;
Srinidhi N Kaushikd801b1f2019-12-27 13:28:01 -0800148}
Subrata Banikbaf6d6e2019-11-01 18:23:33 +0530149
150void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
151{
Srinidhi N Kaushikd801b1f2019-12-27 13:28:01 -0800152 const struct soc_intel_tigerlake_config *config;
153 FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
154
155 config = config_of_soc();
156
157 soc_memory_init_params(m_cfg, config);
158 mainboard_memory_init_params(mupd);
159}
160
161__weak void mainboard_memory_init_params(FSPM_UPD *mupd)
162{
163 printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
Subrata Banikbaf6d6e2019-11-01 18:23:33 +0530164}