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Subrata Banik930c31c2019-11-01 18:12:58 +05301/*
2 * This file is part of the coreboot project.
3 *
Subrata Banikb6df6b02020-01-03 15:29:02 +05304 * Copyright (C) 2019-2020 Intel Corporation.
Subrata Banik930c31c2019-11-01 18:12:58 +05305 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16/*
17 * This file is created based on Intel Tiger Lake Firmware Architecture Specification
18 * Document number: 608531
19 * Chapter number: 4
20 */
21
22#ifndef _SOC_TIGERLAKE_IOMAP_H_
23#define _SOC_TIGERLAKE_IOMAP_H_
24
25/*
26 * Memory-mapped I/O registers.
27 */
28#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
29#define MCFG_BASE_SIZE 0x4000000
30
31#define PCH_PRESERVED_BASE_ADDRESS 0xfc800000
32#define PCH_PRESERVED_BASE_SIZE 0x02000000
33
34#define PCH_TRACE_HUB_BASE_ADDRESS 0xfc800000
35#define PCH_TRACE_HUB_BASE_SIZE 0x00800000
36
Ravi Sarawadifbd68692019-12-16 23:28:36 -080037#define UART_BASE_SIZE 0x1000
Subrata Banik930c31c2019-11-01 18:12:58 +053038
Ravi Sarawadifbd68692019-12-16 23:28:36 -080039#define UART_BASE_0_ADDRESS 0xfe03e000
40/* Both UART BAR 0 and 1 are 4KB in size */
41#define UART_BASE_0_ADDR(x) (UART_BASE_0_ADDRESS + (2 * \
42 UART_BASE_SIZE * (x)))
43#define UART_BASE(x) UART_BASE_0_ADDR(x)
44
Subrata Banik930c31c2019-11-01 18:12:58 +053045#define DMI_BASE_ADDRESS 0xfeda0000
46#define DMI_BASE_SIZE 0x1000
47
48#define EP_BASE_ADDRESS 0xfeda1000
49#define EP_BASE_SIZE 0x1000
50
51#define EDRAM_BASE_ADDRESS 0xfed80000
52#define EDRAM_BASE_SIZE 0x4000
53
John Zhao49111cd2020-01-03 11:01:23 -080054#define TBT0_BASE_ADDRESS 0xfed84000
55#define TBT0_BASE_SIZE 0x1000
56
57#define TBT1_BASE_ADDRESS 0xfed85000
58#define TBT1_BASE_SIZE 0x1000
59
60#define TBT2_BASE_ADDRESS 0xfed86000
61#define TBT2_BASE_SIZE 0x1000
62
63#define TBT3_BASE_ADDRESS 0xfed87000
64#define TBT3_BASE_SIZE 0x1000
65
66#define GFXVT_BASE_ADDRESS 0xfed90000
67#define GFXVT_BASE_SIZE 0x1000
68
69#define IPUVT_BASE_ADDRESS 0xfed92000
70#define IPUVT_BASE_SIZE 0x1000
71
72#define VTVC0_BASE_ADDRESS 0xfed91000
73#define VTVC0_BASE_SIZE 0x1000
74
Ravi Sarawadifbd68692019-12-16 23:28:36 -080075#define REG_BASE_ADDRESS 0xfb000000
Subrata Banik930c31c2019-11-01 18:12:58 +053076#define REG_BASE_SIZE 0x1000
77
78#define HPET_BASE_ADDRESS 0xfed00000
79
80#define PCH_PWRM_BASE_ADDRESS 0xfe000000
81#define PCH_PWRM_BASE_SIZE 0x10000
82
83#define SPI_BASE_ADDRESS 0xfe010000
Subrata Banik930c31c2019-11-01 18:12:58 +053084
85#define GPIO_BASE_SIZE 0x10000
86
87#define HECI1_BASE_ADDRESS 0xfeda2000
88
Ravi Sarawadifbd68692019-12-16 23:28:36 -080089#define VTD_BASE_ADDRESS 0xfed90000
Subrata Banik930c31c2019-11-01 18:12:58 +053090#define VTD_BASE_SIZE 0x00004000
Subrata Banikb6df6b02020-01-03 15:29:02 +053091
92#define ABOVE_4GB_MEM_BASE_ADDRESS (256ULL * GiB)
93#define ABOVE_4GB_MEM_BASE_SIZE (256ULL * GiB)
94
Meera Ravindranathb143e672020-02-07 22:27:58 +053095#if CONFIG(SOC_INTEL_TIGERLAKE)
96
97#define MCH_BASE_ADDRESS 0xfedc0000
98#define MCH_BASE_SIZE 0x20000
99
100#define EARLY_GSPI_BASE_ADDRESS 0xfe030000
101
102#define EARLY_I2C_BASE_ADDRESS 0xfe020000
103#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x2000 * (x)))
104
105#else /* CONFIG_SOC_INTEL_JASPERLAKE */
106
107#define MCH_BASE_ADDRESS 0xfea80000
108#define MCH_BASE_SIZE 0x8000
109
110#define EARLY_GSPI_BASE_ADDRESS 0xfe011000
111
112#define EARLY_I2C_BASE_ADDRESS 0xfe040000
113#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x)))
114
115#endif
116
Subrata Banik930c31c2019-11-01 18:12:58 +0530117/*
118 * I/O port address space
119 */
120#define SMBUS_BASE_ADDRESS 0x0efa0
121#define SMBUS_BASE_SIZE 0x20
122
123#define ACPI_BASE_ADDRESS 0x1800
124#define ACPI_BASE_SIZE 0x100
125
126#define TCO_BASE_ADDRESS 0x400
127#define TCO_BASE_SIZE 0x20
128
129#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS
130#define P2SB_SIZE (16 * MiB)
131
132#endif