blob: 5e5493a3558a1169f2127b05171cd195e37fee9b [file] [log] [blame]
Patrick Georgi11f00792020-03-04 15:10:45 +01001/* SPDX-License-Identifier: GPL-2.0-only */
2/* This file is part of the coreboot project. */
Aaron Durbin956c4f22015-09-05 13:31:14 -05003
4/* This file is included inside a SECTIONS block */
5. = CONFIG_DCACHE_RAM_BASE;
6.car.data . (NOLOAD) : {
Andrey Petrovdd56de92016-02-25 17:22:17 -08007 _car_region_start = . ;
Julius Wernercd49cce2019-03-05 16:53:33 -08008#if CONFIG(PAGING_IN_CACHE_AS_RAM)
Aaron Durbin0f35af82018-04-18 01:00:27 -06009 /* Page table pre-allocation. CONFIG_DCACHE_RAM_BASE should be 4KiB
10 * aligned when using this option. */
11 _pagetables = . ;
12 . += 4096 * CONFIG_NUM_CAR_PAGE_TABLE_PAGES;
13 _epagetables = . ;
14#endif
Joel Kitchingd6f71d02019-02-21 12:37:55 +080015 /* Vboot work buffer only needs to be available when verified boot
16 * starts in bootblock. */
Julius Wernercd49cce2019-03-05 16:53:33 -080017#if CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)
Joel Kitching0097f552019-02-21 12:36:55 +080018 VBOOT2_WORK(., 12K)
Aaron Durbin75c51d92015-09-29 16:31:20 -050019#endif
Philipp Deppenwiesec9b7d1f2018-11-10 00:35:02 +010020 /* Vboot measured boot TCPA log measurements.
21 * Needs to be transferred until CBMEM is available
22 */
Arthur Heymans3c613042019-04-21 23:59:47 +020023#if CONFIG(VBOOT_MEASURED_BOOT)
Philipp Deppenwiesec9b7d1f2018-11-10 00:35:02 +010024 VBOOT2_TPM_LOG(., 2K)
Arthur Heymans3c613042019-04-21 23:59:47 +020025#endif
Andrey Petrovee9e4ae2016-02-08 17:17:05 -080026 /* Stack for CAR stages. Since it persists across all stages that
27 * use CAR it can be reused. The chipset/SoC is expected to provide
28 * the stack size. */
Arthur Heymansdf9cdcf2019-11-09 06:50:20 +010029 _car_stack = .;
Andrey Petrovee9e4ae2016-02-08 17:17:05 -080030 . += CONFIG_DCACHE_BSP_STACK_SIZE;
Arthur Heymansdf9cdcf2019-11-09 06:50:20 +010031 _ecar_stack = .;
Aaron Durbindd6fa932015-09-24 12:18:07 -050032 /* The pre-ram cbmem console as well as the timestamp region are fixed
Arthur Heymans4cc9b6c2018-12-28 17:53:36 +010033 * in size. Therefore place them above the car global section so that
34 * multiple stages (romstage and verstage) have a consistent
35 * link address of these shared objects. */
Kyösti Mälkki513a1a82018-06-03 12:29:50 +030036 PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE)
Julius Wernercd49cce2019-03-05 16:53:33 -080037#if CONFIG(PAGING_IN_CACHE_AS_RAM)
Aaron Durbin0f35af82018-04-18 01:00:27 -060038 . = ALIGN(32);
39 /* Page directory pointer table resides here. There are 4 8-byte entries
40 * totalling 32 bytes that need to be 32-byte aligned. The reason the
41 * pdpt are not colocated with the rest of the page tables is to reduce
42 * fragmentation of the CAR space that persists across stages. */
43 _pdpt = .;
44 . += 32;
45 _epdpt = .;
46#endif
Kyösti Mälkki3dd23a52019-08-22 15:06:50 +030047
Furquan Shaikh549080b2018-05-17 23:30:28 -070048 TIMESTAMP(., 0x200)
Julius Werner7fc92862019-11-18 13:01:06 -080049
50#if !CONFIG(NO_FMAP_CACHE)
Julius Wernercefe89e2019-11-06 19:29:44 -080051 FMAP_CACHE(., FMAP_SIZE)
Julius Werner7fc92862019-11-18 13:01:06 -080052#endif
Kyösti Mälkki3dd23a52019-08-22 15:06:50 +030053
Arthur Heymansdf9cdcf2019-11-09 06:50:20 +010054 _car_ehci_dbg_info = .;
Kyösti Mälkkif88208e2019-01-31 08:29:32 +020055 /* Reserve sizeof(struct ehci_dbg_info). */
Kyösti Mälkki45ad4f02019-01-31 19:24:04 +020056 . += 80;
Arthur Heymansdf9cdcf2019-11-09 06:50:20 +010057 _ecar_ehci_dbg_info = .;
Kyösti Mälkki3dd23a52019-08-22 15:06:50 +030058
Kyösti Mälkki910490f2019-08-22 12:56:22 +030059 /* _bss and _ebss provide symbols to per-stage
Aaron Durbindd6fa932015-09-24 12:18:07 -050060 * variables that are not shared like the timestamp and the pre-ram
61 * cbmem console. This is useful for clearing this area on a per-stage
Arthur Heymansfdb8b132019-11-28 14:00:01 +010062 * basis when more than one stage uses cache-as-ram. */
Kyösti Mälkki910490f2019-08-22 12:56:22 +030063
64 . = ALIGN(ARCH_POINTER_ALIGN_SIZE);
65 _bss = .;
Kyösti Mälkkia165c072019-08-22 09:44:44 +030066#if ENV_STAGE_HAS_BSS_SECTION
67 /* Allow global uninitialized variables for stages without CAR teardown. */
Aaron Durbin76ab2b72018-10-30 12:15:10 -060068 *(.bss)
69 *(.bss.*)
70 *(.sbss)
71 *(.sbss.*)
Aaron Durbin76ab2b72018-10-30 12:15:10 -060072#endif
Aaron Durbin956c4f22015-09-05 13:31:14 -050073 . = ALIGN(ARCH_POINTER_ALIGN_SIZE);
Kyösti Mälkki910490f2019-08-22 12:56:22 +030074 _ebss = .;
Kyösti Mälkki1095bfa2019-08-22 12:56:22 +030075 _car_unallocated_start = .;
Andrey Petrovdd56de92016-02-25 17:22:17 -080076
77 _car_region_end = . + CONFIG_DCACHE_RAM_SIZE - (. - _car_region_start);
Aaron Durbin956c4f22015-09-05 13:31:14 -050078}
79
80/* Global variables are not allowed in romstage
81 * This section is checked during stage creation to ensure
82 * that there are no global variables present
83 */
84
85. = 0xffffff00;
86.illegal_globals . : {
Nico Huber98fc4262016-01-23 01:24:33 +010087 *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data)
88 *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*)
Aaron Durbin956c4f22015-09-05 13:31:14 -050089}
90
Aaron Durbindd6fa932015-09-24 12:18:07 -050091_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
Julius Wernercd49cce2019-03-05 16:53:33 -080092#if CONFIG(PAGING_IN_CACHE_AS_RAM)
Aaron Durbin0f35af82018-04-18 01:00:27 -060093_bogus2 = ASSERT(_pagetables == ALIGN(_pagetables, 4096), "_pagetables aren't 4KiB aligned");
94#endif
Patrick Rudolphd72d52a2018-11-12 19:26:54 +010095_bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured");