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Andrey Petrovf35804b2017-06-05 13:22:41 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2008 coresystems GmbH
5 * Copyright (C) 2014 Google Inc.
6 * Copyright (C) 2017 Intel Corporation.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#ifndef SOC_CANNONLAKE_SYSTEMAGENT_H
19#define SOC_CANNONLAKE_SYSTEMAGENT_H
20
21#include <intelblocks/systemagent.h>
22#include <soc/iomap.h>
23
24/* Device 0:0.0 PCI configuration space */
25
26#define EPBAR 0x40
27#define PCIEXBAR 0x60
28#define DMIBAR 0x68
29#define GGC 0x50 /* GMCH Graphics Control */
30#define DEVEN 0x54 /* Device Enable */
31#define DEVEN_D7EN (1 << 14)
32#define DEVEN_D4EN (1 << 7)
33#define DEVEN_D3EN (1 << 5)
34#define DEVEN_D2EN (1 << 4)
35#define DEVEN_D1F0EN (1 << 3)
36#define DEVEN_D1F1EN (1 << 2)
37#define DEVEN_D1F2EN (1 << 1)
38#define DEVEN_D0EN (1 << 0)
39#define DPR 0x5c
40#define DPR_EPM (1 << 2)
41#define DPR_PRS (1 << 1)
42#define DPR_SIZE_MASK 0xff0
43
44#define PAM0 0x80
45#define PAM1 0x81
46#define PAM2 0x82
47#define PAM3 0x83
48#define PAM4 0x84
49#define PAM5 0x85
50#define PAM6 0x86
51
52#define SMRAM 0x88 /* System Management RAM Control */
53#define D_OPEN (1 << 6)
54#define D_CLS (1 << 5)
55#define D_LCK (1 << 4)
56#define G_SMRAME (1 << 3)
57#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
58
59#define MESEG_BASE 0x70 /* Management Engine Base. */
60#define MESEG_LIMIT 0x78 /* Management Engine Limit. */
61#define TOM 0xa0 /* Top of DRAM in memory controller space. */
62#define SKPAD 0xdc /* Scratchpad Data */
63
64/* MCHBAR */
65
66#define MCHBAR8(x) (*(volatile u8 *)(MCH_BASE_ADDRESS + x))
67#define MCHBAR16(x) (*(volatile u16 *)(MCH_BASE_ADDRESS + x))
68#define MCHBAR32(x) (*(volatile u32 *)(MCH_BASE_ADDRESS + x))
69
70#define MCHBAR_PEI_VERSION 0x5034
71#define REMAPBASE 0x5090 /* Remap base. */
72#define REMAPLIMIT 0x5098 /* Remap limit. */
73#define BIOS_RESET_CPL 0x5da8
74#define EDRAMBAR 0x5408
75#define MCH_PAIR 0x5418
76#define REGBAR 0x5420
77
78#define MCH_PKG_POWER_LIMIT_LO 0x59a0
79#define MCH_PKG_POWER_LIMIT_HI 0x59a4
80#define MCH_DDR_POWER_LIMIT_LO 0x58e0
81#define MCH_DDR_POWER_LIMIT_HI 0x58e4
82
83/* PCODE MMIO communications live in the MCHBAR. */
84#define BIOS_MAILBOX_INTERFACE 0x5da4
85#define MAILBOX_RUN_BUSY (1 << 31)
86/* Errors are returned back in bits 7:0. */
87#define MAILBOX_BIOS_ERROR_NONE 0
88#define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1
89#define MAILBOX_BIOS_ERROR_TIMEOUT 2
90#define MAILBOX_BIOS_ERROR_ILLEGAL_DATA 3
91#define MAILBOX_BIOS_ERROR_RESERVED 4
92#define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5
93#define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6
94#define MAILBOX_BIOS_ERROR_VR_ERROR 7
95/* Data is passed through bits 31:0 of the data register. */
96#define BIOS_MAILBOX_DATA 0x5da0
97
98/* System Agent identification */
99u8 systemagent_revision(void);
100
Andrey Petrovf35804b2017-06-05 13:22:41 -0700101#endif