blob: 9de6981d5aa2152d53a8a3fd1826e5b623bca6fc [file] [log] [blame]
Andrey Petrovf35804b2017-06-05 13:22:41 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com>
5 * Copyright (C) 2009 coresystems GmbH
6 * Copyright (C) 2014 Google Inc.
7 * Copyright (C) 2017 Intel Corporation.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef _SOC_CANNONLAKE_SMBUS_H_
20#define _SOC_CANNONLAKE_SMBUS_H_
21
22/* PCI registers */
23#define TCOBASE 0x50 /* TCO base address. */
24#define TCOCTL 0x54
25#define TCO_BASE_EN (1 << 8) /* TCO base enable. */
26
27/* IO and MMIO registers under primary BAR */
28/* Set address for PCH as SMBus slave role */
29#define SMB_RCV_SLVA 0x09
30
31/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
32#define TCO1_STS 0x04
33#define TCO2_STS 0x06
34#define TCO2_STS_SECOND_TO 0x02
35#define TCO2_STS_BOOT 0x04
36#define TCO1_CNT 0x08
37#define TCO_LOCK (1 << 12)
38#define TCO_TMR_HLT (1 << 11)
39
40/*
41 * Default slave address value for PCH. This value is set to match default
42 * value set by hardware. It is useful since PCH is able to respond even
43 * before CPU is up. This is reset by RSMRST# but not by PLTRST#.
44 */
45#define SMBUS_SLAVE_ADDR 0x44
46
47#endif