blob: 0bca332ac5cbada80f365d74aa6ea424d4d5cc46 [file] [log] [blame]
Andrey Petrov60a7e782017-06-05 14:11:32 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2014 Google Inc.
5 * Copyright (C) 2017 Intel Corporation.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#ifndef _SOC_CANNONLAKE_PMC_H_
18#define _SOC_CANNONLAKE_PMC_H_
19
20/* PCI Configuration Space (D31:F2): PMC */
21#define PWRMBASE 0x10
22#define ABASE 0x20
23
24/* Memory mapped IO registers in PMC */
25#define GEN_PMCON_A 0x1020
26#define DC_PP_DIS (1 << 30)
27#define DSX_PP_DIS (1 << 29)
28#define AG3_PP_EN (1 << 28)
29#define SX_PP_EN (1 << 27)
30#define ALLOW_ICLK_PLL_SD_INC0 (1 << 26)
31#define GBL_RST_STS (1 << 24)
32#define DISB (1 << 23)
33#define ALLOW_OPI_PLL_SD_INC0 (1 << 22)
34#define MEM_SR (1 << 21)
35#define ALLOW_SPXB_CG_INC0 (1 << 20)
36#define ALLOW_L1LOW_C0 (1 << 19)
37#define MS4V (1 << 18)
38#define ALLOW_L1LOW_OPI_ON (1 << 17)
39#define SUS_PWR_FLR (1 << 16)
40#define PME_B0_S5_DIS (1 << 15)
41#define PWR_FLR (1 << 14)
42#define ALLOW_L1LOW_BCLKREQ_ON (1 << 13)
43#define DIS_SLP_X_STRCH_SUS_UP (1 << 12)
44#define SLP_S3_MIN_ASST_WDTH_MASK (3 << 10)
45#define SLP_S3_MIN_ASST_WDTH_60USEC (0 << 10)
46#define SLP_S3_MIN_ASST_WDTH_1MS (1 << 10)
47#define SLP_S3_MIN_ASST_WDTH_50MS (2 << 10)
48#define SLP_S3_MIN_ASST_WDTH_2S (3 << 10)
49#define HOST_RST_STS (1 << 9)
50#define ESPI_SMI_LOCK (1 << 8)
51#define S4MAW_MASK (3 << 4)
52#define S4MAW_1S (1 << 4)
53#define S4MAW_2S (2 << 4)
54#define S4MAW_3S (3 << 4)
55#define S4MAW_4S (0 << 4)
56#define S4ASE (1 << 3)
57#define PER_SMI_SEL_MASK (3 << 1)
58#define SMI_RATE_64S (0 << 1)
59#define SMI_RATE_32S (1 << 1)
60#define SMI_RATE_16S (2 << 1)
61#define SMI_RATE_8S (3 << 1)
62#define SLEEP_AFTER_POWER_FAIL (1 << 0)
63
64#define GEN_PMCON_B 0x1024
65#define SLP_STR_POL_LOCK (1 << 18)
66#define ACPI_BASE_LOCK (1 << 17)
67#define PM_DATA_BAR_DIS (1 << 16)
68#define WOL_EN_OVRD (1 << 13)
69#define BIOS_PCI_EXP_EN (1 << 10)
70#define PWRBTN_LVL (1 << 9)
71#define SMI_LOCK (1 << 4)
72#define RTC_BATTERY_DEAD (1 << 2)
73
74#define ETR3 0x1048
75#define ETR3_CF9LOCK (1 << 31)
76#define ETR3_CF9GR (1 << 20)
77
78#define SSML 0x104C
79#define SSML_SSL_DS (0 << 0)
80#define SSML_SSL_EN (1 << 0)
81
82#define SSMC 0x1050
83#define SSMC_SSMS (1 << 0)
84
85#define SSMD 0x1054
86#define SSMD_SSD_MASK (0xffff << 0)
87
88#define S3_PWRGATE_POL 0x1828
89#define S3DC_GATE_SUS (1 << 1)
90#define S3AC_GATE_SUS (1 << 0)
91
92#define S4_PWRGATE_POL 0x182c
93#define S4DC_GATE_SUS (1 << 1)
94#define S4AC_GATE_SUS (1 << 0)
95
96#define S5_PWRGATE_POL 0x1830
97#define S5DC_GATE_SUS (1 << 15)
98#define S5AC_GATE_SUS (1 << 14)
99
100#define DSX_CFG 0x1834
101#define REQ_CNV_NOWAKE_DSX (1 << 4)
102#define REQ_BATLOW_DSX (1 << 3)
103#define DSX_EN_WAKE_PIN (1 << 2)
104#define DSX_EN_AC_PRESENT_PIN (1 << 1)
105#define DSX_EN_LAN_WAKE_PIN (1 << 0)
106
107#define PMSYNC_TPR_CFG 0x18C4
108#define PCH2CPU_TPR_CFG_LOCK (1 << 31)
109#define PCH2CPU_TT_EN (1 << 26)
110
111#define PCH_PWRM_ACPI_TMR_CTL 0x18FC
112#define GPIO_CFG 0x1920
113#define GPE0_DWX_MASK 0xf
114#define GPE0_DW0_SHIFT 0
115#define GPE0_DW1_SHIFT 4
116#define GPE0_DW2_SHIFT 8
117
118#define GBLRST_CAUSE0 0x1924
119#define GBLRST_CAUSE0_THERMTRIP (1 << 5)
120#define GBLRST_CAUSE1 0x1928
121
122#define ACTL 0x1BD8
123#define PWRM_EN (1 << 8)
124#define ACPI_EN (1 << 7)
125#define SCI_IRQ_SEL (7 << 0)
126
127#define SCIS_IRQ9 0
128#define SCIS_IRQ10 1
129#define SCIS_IRQ11 2
130#define SCIS_IRQ20 4
131#define SCIS_IRQ21 5
132#define SCIS_IRQ22 6
133#define SCIS_IRQ23 7
134#endif