blob: 931281a5c916eacbb3b7ddecfb10f4c3f1ff6c65 [file] [log] [blame]
Andrey Petrov3e2e0502017-06-05 13:22:24 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2014 Google Inc.
5 * Copyright (C) 2017 Intel Corporation.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#ifndef _SOC_MSR_H_
18#define _SOC_MSR_H_
19
20#include <intelblocks/msr.h>
21
22#define MSR_PIC_MSG_CONTROL 0x2e
23#define MSR_BIOS_UPGD_TRIG 0x7a
24#define IA32_THERM_INTERRUPT 0x19b
25#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
26#define ENERGY_POLICY_PERFORMANCE 0
27#define ENERGY_POLICY_NORMAL 6
28#define ENERGY_POLICY_POWERSAVE 15
29#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
30#define PRMRR_PHYS_BASE_MSR 0x1f4
31#define IA32_PLATFORM_DCA_CAP 0x1f8
32#define MSR_LT_LOCK_MEMORY 0x2e7
33#define MSR_SGX_OWNEREPOCH0 0x300
34#define MSR_SGX_OWNEREPOCH1 0x301
35#define MSR_VR_CURRENT_CONFIG 0x601
36#define MSR_VR_MISC_CONFIG 0x603
37#define MSR_VR_MISC_CONFIG2 0x636
38#define MSR_PP0_POWER_LIMIT 0x638
39#define MSR_PP1_POWER_LIMIT 0x640
40
41#endif