blob: 3488ee2b850ebfc3fb9b1dedecabde34bb153ab2 [file] [log] [blame]
Andrey Petrovf35804b2017-06-05 13:22:41 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2014 Google Inc.
5 * Copyright (C) 2017 Intel Corporation.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#ifndef _SOC_CANNONLAKE_LPC_H_
18#define _SOC_CANNONLAKE_LPC_H_
19
20/* PCI Configuration Space (D31:F0): LPC */
21#define SCI_IRQ_SEL (7 << 0)
22#define SCIS_IRQ9 0
23#define SCIS_IRQ10 1
24#define SCIS_IRQ11 2
25#define SCIS_IRQ20 4
26#define SCIS_IRQ21 5
27#define SCIS_IRQ22 6
28#define SCIS_IRQ23 7
29#define SERIRQ_CNTL 0x64
30#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */
31#define COMA_RANGE 0x0 /* 0x3F8 - 0x3FF COM1*/
32#define COMB_RANGE 0x1 /* 0x2F8 - 0x2FF COM2*/
33#define LPC_EN 0x82 /* LPC IF Enables Register */
34#define MC2_LPC_EN (1 << 13) /* 0x4e/0x4f */
35#define SE_LPC_EN (1 << 12) /* 0x2e/0x2f */
36#define MC1_LPC_EN (1 << 11) /* 0x62/0x66 */
37#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */
38#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */
39#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */
40#define FDD_LPC_EN (1 << 3) /* Floppy Drive Enable */
41#define LPT_LPC_EN (1 << 2) /* Parallel Port Enable */
42#define COMB_LPC_EN (1 << 1) /* Com Port B Enable */
43#define COMA_LPC_EN (1 << 0) /* Com Port A Enable */
44#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */
45#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */
46#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */
47#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */
48#define LGMR 0x98 /* LPC Generic Memory Range */
49#define BIOS_CNTL 0xdc
50#define LPC_BC_BILD (1 << 7) /* BILD */
51#define LPC_BC_LE (1 << 2) /* LE */
52#define LPC_BC_EISS (1 << 5) /* EISS */
53#define PCCTL 0xE0 /* PCI Clock Control */
54#define CLKRUN_EN (1 << 0)
55#endif