blob: c2bb0500db52285f6177f4ec4db016c1967ede93 [file] [log] [blame]
Andrey Petrovab85e2b2017-06-05 13:21:48 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2014 Google Inc.
5 * Copyright (C) 2017 Intel Corporation.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#ifndef _SOC_CANNONLAKE_IOMAP_H_
18#define _SOC_CANNONLAKE_IOMAP_H_
19
20/*
21 * Memory-mapped I/O registers.
22 */
23#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
24#define MCFG_BASE_SIZE 0x4000000
25
26#define PCH_PRESERVED_BASE_ADDRESS 0xfc800000
27#define PCH_PRESERVED_BASE_SIZE 0x02000000
28
29#define PCH_TRACE_HUB_BASE_ADDRESS 0xfc800000
30#define PCH_TRACE_HUB_BASE_SIZE 0x00800000
31#define UART_DEBUG_BASE_ADDRESS 0xfe036000
32#define UART_DEBUG_BASE_SIZE 0x1000
33
34#define EARLY_I2C_BASE_ADDRESS 0xfe040000
35#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x)))
36
37#define MCH_BASE_ADDRESS 0xfed10000
38#define MCH_BASE_SIZE 0x8000
39
40#define DMI_BASE_ADDRESS 0xfeda0000
41#define DMI_BASE_SIZE 0x1000
42
43#define EP_BASE_ADDRESS 0xfeda1000
44#define EP_BASE_SIZE 0x1000
45
46#define EDRAM_BASE_ADDRESS 0xfed80000
47#define EDRAM_BASE_SIZE 0x4000
48
49#define REG_BASE_ADDRESS 0xfc000000
50#define REG_BASE_SIZE 0x1000
51
52#define HPET_BASE_ADDRESS 0xfed00000
53
54#define PCH_PWRM_BASE_ADDRESS 0xfe000000
55#define PCH_PWRM_BASE_SIZE 0x10000
56
57#define SPI_BASE_ADDRESS 0xfe010000
58#define EARLY_GSPI_BASE_ADDRESS 0xfe011000
59
60#define GPIO_BASE_SIZE 0x10000
61
62#define HECI1_BASE_ADDRESS 0xFEDA2000
63
64/* CPU Trace reserved memory size */
65#define TRACE_MEMORY_SIZE 0x8000000 /* 128MiB */
66
67/*
68 * I/O port address space
69 */
70#define SMBUS_BASE_ADDRESS 0x0efa0
71#define SMBUS_BASE_SIZE 0x20
72
73#define ACPI_BASE_ADDRESS 0x1800
74#define ACPI_BASE_SIZE 0x100
75
76#define TCO_BASE_ADDRESS 0x400
77#define TCO_BASE_SIZE 0x20
78
79#endif