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Andrey Petrovc854b492017-06-05 14:10:17 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2017 Intel Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef _SOC_CANNONLAKE_GPIO_DEFS_H_
17#define _SOC_CANNONLAKE_GPIO_DEFS_H_
18
19#ifndef __ACPI__
20#include <stddef.h>
21#endif
22#include <soc/gpio_soc_defs.h>
23
24
25#define GPIO_NUM_PAD_CFG_REGS 2 /* DW0, DW1 */
26
27#define NUM_GPIO_COMx_GPI_REGS(n) \
28 (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
29
30#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS)
31#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS)
32#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS)
33#define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM3_PADS)
34
35#define NUM_GPI_STATUS_REGS \
36 ((NUM_GPIO_COM0_GPI_REGS) +\
37 (NUM_GPIO_COM1_GPI_REGS) +\
38 (NUM_GPIO_COM2_GPI_REGS) +\
39 (NUM_GPIO_COM3_GPI_REGS))
40/*
41 * IOxAPIC IRQs for the GPIOs
42 */
43
44/* Group A */
45#define GPP_A0_IRQ 0x18
46#define GPP_A1_IRQ 0x19
47#define GPP_A2_IRQ 0x1a
48#define GPP_A3_IRQ 0x1b
49#define GPP_A4_IRQ 0x1c
50#define GPP_A5_IRQ 0x1d
51#define GPP_A6_IRQ 0x1e
52#define GPP_A7_IRQ 0x1f
53#define GPP_A8_IRQ 0x20
54#define GPP_A9_IRQ 0x21
55#define GPP_A10_IRQ 0x22
56#define GPP_A11_IRQ 0x23
57#define GPP_A12_IRQ 0x24
58#define GPP_A13_IRQ 0x25
59#define GPP_A14_IRQ 0x26
60#define GPP_A15_IRQ 0x27
61#define GPP_A16_IRQ 0x28
62#define GPP_A17_IRQ 0x29
63#define GPP_A18_IRQ 0x2a
64#define GPP_A19_IRQ 0x2b
65#define GPP_A20_IRQ 0x2c
66#define GPP_A21_IRQ 0x2d
67#define GPP_A22_IRQ 0x2e
68#define GPP_A23_IRQ 0x2f
69/* Group B */
70#define GPP_B0_IRQ 0x30
71#define GPP_B1_IRQ 0x31
72#define GPP_B2_IRQ 0x32
73#define GPP_B3_IRQ 0x33
74#define GPP_B4_IRQ 0x34
75#define GPP_B5_IRQ 0x35
76#define GPP_B6_IRQ 0x36
77#define GPP_B7_IRQ 0x37
78#define GPP_B8_IRQ 0x38
79#define GPP_B9_IRQ 0x39
80#define GPP_B10_IRQ 0x3a
81#define GPP_B11_IRQ 0x3b
82#define GPP_B12_IRQ 0x3c
83#define GPP_B13_IRQ 0x3d
84#define GPP_B14_IRQ 0x3e
85#define GPP_B15_IRQ 0x3f
86#define GPP_B16_IRQ 0x40
87#define GPP_B17_IRQ 0x41
88#define GPP_B18_IRQ 0x42
89#define GPP_B19_IRQ 0x43
90#define GPP_B20_IRQ 0x44
91#define GPP_B21_IRQ 0x45
92#define GPP_B22_IRQ 0x46
93#define GPP_B23_IRQ 0x47
94/* Group C */
95#define GPP_C0_IRQ 0x48
96#define GPP_C1_IRQ 0x49
97#define GPP_C2_IRQ 0x4a
98#define GPP_C3_IRQ 0x4b
99#define GPP_C4_IRQ 0x4c
100#define GPP_C5_IRQ 0x4d
101#define GPP_C6_IRQ 0x4e
102#define GPP_C7_IRQ 0x4f
103#define GPP_C8_IRQ 0x50
104#define GPP_C9_IRQ 0x51
105#define GPP_C10_IRQ 0x52
106#define GPP_C11_IRQ 0x53
107#define GPP_C12_IRQ 0x54
108#define GPP_C13_IRQ 0x55
109#define GPP_C14_IRQ 0x56
110#define GPP_C15_IRQ 0x57
111#define GPP_C16_IRQ 0x58
112#define GPP_C17_IRQ 0x59
113#define GPP_C18_IRQ 0x5a
114#define GPP_C19_IRQ 0x5b
115#define GPP_C20_IRQ 0x5c
116#define GPP_C21_IRQ 0x5d
117#define GPP_C22_IRQ 0x5e
118#define GPP_C23_IRQ 0x5f
119/* Group D */
120#define GPP_D0_IRQ 0x60
121#define GPP_D1_IRQ 0x61
122#define GPP_D2_IRQ 0x62
123#define GPP_D3_IRQ 0x63
124#define GPP_D4_IRQ 0x64
125#define GPP_D5_IRQ 0x65
126#define GPP_D6_IRQ 0x66
127#define GPP_D7_IRQ 0x67
128#define GPP_D8_IRQ 0x68
129#define GPP_D9_IRQ 0x69
130#define GPP_D10_IRQ 0x6a
131#define GPP_D11_IRQ 0x6b
132#define GPP_D12_IRQ 0x6c
133#define GPP_D13_IRQ 0x6d
134#define GPP_D14_IRQ 0x6e
135#define GPP_D15_IRQ 0x6f
136#define GPP_D16_IRQ 0x70
137#define GPP_D17_IRQ 0x71
138#define GPP_D18_IRQ 0x72
139#define GPP_D19_IRQ 0x73
140#define GPP_D20_IRQ 0x74
141#define GPP_D21_IRQ 0x75
142#define GPP_D22_IRQ 0x76
143#define GPP_D23_IRQ 0x77
144/* Group E */
145#define GPP_E0_IRQ 0x18
146#define GPP_E1_IRQ 0x19
147#define GPP_E2_IRQ 0x1a
148#define GPP_E3_IRQ 0x1b
149#define GPP_E4_IRQ 0x1c
150#define GPP_E5_IRQ 0x1d
151#define GPP_E6_IRQ 0x1e
152#define GPP_E7_IRQ 0x1f
153#define GPP_E8_IRQ 0x20
154#define GPP_E9_IRQ 0x21
155#define GPP_E10_IRQ 0x22
156#define GPP_E11_IRQ 0x23
157#define GPP_E12_IRQ 0x24
158#define GPP_E13_IRQ 0x25
159#define GPP_E14_IRQ 0x26
160#define GPP_E15_IRQ 0x27
161#define GPP_E16_IRQ 0x28
162#define GPP_E17_IRQ 0x29
163#define GPP_E18_IRQ 0x2a
164#define GPP_E19_IRQ 0x2b
165#define GPP_E20_IRQ 0x2c
166#define GPP_E21_IRQ 0x2d
167#define GPP_E22_IRQ 0x2e
168#define GPP_E23_IRQ 0x2f
169/* Group F */
170#define GPP_F0_IRQ 0x30
171#define GPP_F1_IRQ 0x31
172#define GPP_F2_IRQ 0x32
173#define GPP_F3_IRQ 0x33
174#define GPP_F4_IRQ 0x34
175#define GPP_F5_IRQ 0x35
176#define GPP_F6_IRQ 0x36
177#define GPP_F7_IRQ 0x37
178#define GPP_F8_IRQ 0x38
179#define GPP_F9_IRQ 0x39
180#define GPP_F10_IRQ 0x3a
181#define GPP_F11_IRQ 0x3b
182#define GPP_F12_IRQ 0x3c
183#define GPP_F13_IRQ 0x3d
184#define GPP_F14_IRQ 0x3e
185#define GPP_F15_IRQ 0x3f
186#define GPP_F16_IRQ 0x40
187#define GPP_F17_IRQ 0x41
188#define GPP_F18_IRQ 0x42
189#define GPP_F19_IRQ 0x43
190#define GPP_F20_IRQ 0x44
191#define GPP_F21_IRQ 0x45
192#define GPP_F22_IRQ 0x46
193#define GPP_F23_IRQ 0x47
194/* Group G */
195#define GPP_G0_IRQ 0x6c
196#define GPP_G1_IRQ 0x6d
197#define GPP_G2_IRQ 0x6e
198#define GPP_G3_IRQ 0x6f
199#define GPP_G4_IRQ 0x70
200#define GPP_G5_IRQ 0x71
201#define GPP_G6_IRQ 0x72
202#define GPP_G7_IRQ 0x73
203/* Group GPD */
204#define GPD0_IRQ 0x60
205#define GPD1_IRQ 0x61
206#define GPD2_IRQ 0x62
207#define GPD3_IRQ 0x63
208#define GPD4_IRQ 0x64
209#define GPD5_IRQ 0x65
210#define GPD6_IRQ 0x66
211#define GPD7_IRQ 0x67
212#define GPD8_IRQ 0x68
213#define GPD9_IRQ 0x69
214#define GPD10_IRQ 0x6a
215#define GPD11_IRQ 0x6b
216/* Group H */
217#define GPP_H0_IRQ 0x48
218#define GPP_H1_IRQ 0x49
219#define GPP_H2_IRQ 0x4a
220#define GPP_H3_IRQ 0x4b
221#define GPP_H4_IRQ 0x4c
222#define GPP_H5_IRQ 0x4d
223#define GPP_H6_IRQ 0x4e
224#define GPP_H7_IRQ 0x4f
225#define GPP_H8_IRQ 0x50
226#define GPP_H9_IRQ 0x51
227#define GPP_H10_IRQ 0x52
228#define GPP_H11_IRQ 0x53
229#define GPP_H12_IRQ 0x54
230#define GPP_H13_IRQ 0x55
231#define GPP_H14_IRQ 0x56
232#define GPP_H15_IRQ 0x57
233#define GPP_H16_IRQ 0x58
234#define GPP_H17_IRQ 0x59
235#define GPP_H18_IRQ 0x5a
236#define GPP_H19_IRQ 0x5b
237#define GPP_H20_IRQ 0x5c
238#define GPP_H21_IRQ 0x5d
239#define GPP_H22_IRQ 0x5e
240#define GPP_H23_IRQ 0x5f
241
242/* Register defines. */
243#define GPIO_MISCCFG 0x10
244#define GPE_DW_SHIFT 8
245#define GPE_DW_MASK 0xfff00
246#define HOSTSW_OWN_REG_0 0xb0
247#define GPI_SMI_STS_0 0x180
248#define GPI_SMI_EN_0 0x1A0
249#define PAD_CFG_BASE 0x600
250
251#endif