blob: 2dd90f9f0166fc00d201220d4522c941d8394475 [file] [log] [blame]
Andrey Petrovc854b492017-06-05 14:10:17 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2015 - 2017 Intel Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <intelblocks/gpio.h>
18#include <intelblocks/pcr.h>
19#include <soc/pcr_ids.h>
20
21static const struct reset_mapping rst_map[] = {
22 { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 },
23 { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
24 { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
25};
26
27static const struct reset_mapping rst_map_com0[] = {
28 { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
29 { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
30 { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
31 { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 },
32};
33
34static const struct pad_community cnl_communities[] = {
35 { /* GPP A, B, G */
36 .port = PID_GPIOCOM0,
37 .first_pad = GPP_A0,
38 .last_pad = GPP_G7,
39 .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
40 .pad_cfg_base = PAD_CFG_BASE,
41 .host_own_reg_0 = HOSTSW_OWN_REG_0,
42 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
43 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
44 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
45 .name = "GPP_ABG",
46 .acpi_path = "\\_SB.PCI0.GPIO",
47 .reset_map = rst_map_com0,
48 .num_reset_vals = ARRAY_SIZE(rst_map_com0),
49 }, { /* GPP D, F, H */
50 .port = PID_GPIOCOM1,
51 .first_pad = GPP_D0,
52 .last_pad = GPP_H23,
53 .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
54 .pad_cfg_base = PAD_CFG_BASE,
55 .host_own_reg_0 = HOSTSW_OWN_REG_0,
56 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
57 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
58 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
59 .name = "GPP_DFH",
60 .acpi_path = "\\_SB.PCI0.GPIO",
61 .reset_map = rst_map,
62 .num_reset_vals = ARRAY_SIZE(rst_map),
63 }, { /* GPD */
64 .port = PID_GPIOCOM2,
65 .first_pad = GPD0,
66 .last_pad = GPD11,
67 .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS,
68 .pad_cfg_base = PAD_CFG_BASE,
69 .host_own_reg_0 = HOSTSW_OWN_REG_0,
70 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
71 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
72 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
73 .name = "GPD",
74 .acpi_path = "\\_SB.PCI0.GPIO",
75 .reset_map = rst_map,
76 .num_reset_vals = ARRAY_SIZE(rst_map),
77 }, { /* GPP C, E */
78 .port = PID_GPIOCOM3,
79 .first_pad = GPP_C0,
80 .last_pad = GPP_E23,
81 .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
82 .pad_cfg_base = PAD_CFG_BASE,
83 .host_own_reg_0 = HOSTSW_OWN_REG_0,
84 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
85 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
86 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
87 .name = "GPP_CE",
88 .acpi_path = "\\_SB.PCI0.GPIO",
89 .reset_map = rst_map,
90 .num_reset_vals = ARRAY_SIZE(rst_map),
91 }
92};
93
94const struct pad_community *soc_gpio_get_community(size_t *num_communities)
95{
96 *num_communities = ARRAY_SIZE(cnl_communities);
97 return cnl_communities;
98}