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Piotr Króldcd2f172016-05-27 12:04:13 +02001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <arch/acpi.h>
17#include <arch/io.h>
18#include <console/console.h>
Piotr Króldcd2f172016-05-27 12:04:13 +020019#include <device/device.h>
20#include <device/pci.h>
21#include <device/pci_def.h>
Piotr Króldcd2f172016-05-27 12:04:13 +020022#include <southbridge/amd/pi/hudson/hudson.h>
23#include <southbridge/amd/pi/hudson/pci_devs.h>
24#include <southbridge/amd/pi/hudson/amd_pci_int_defs.h>
25#include <northbridge/amd/pi/00730F01/pci_devs.h>
26#include <southbridge/amd/common/amd_pci_util.h>
27#include <superio/nuvoton/nct5104d/nct5104d.h>
Kyösti Mälkki10407492017-01-16 19:59:52 +020028#include <smbios.h>
29#include <string.h>
Piotr Króldcd2f172016-05-27 12:04:13 +020030#include <cpu/x86/msr.h>
31#include <cpu/amd/mtrr.h>
Kyösti Mälkki10407492017-01-16 19:59:52 +020032#include "gpio_ftns.h"
Piotr Króldcd2f172016-05-27 12:04:13 +020033
34#define SPD_SIZE 128
35#define PM_RTC_CONTROL 0x56
36#define PM_S_STATE_CONTROL 0xBA
37
38
39/***********************************************************
40 * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
41 * This table is responsible for physically routing the PIC and
42 * IOAPIC IRQs to the different PCI devices on the system. It
43 * is read and written via registers 0xC00/0xC01 as an
44 * Index/Data pair. These values are chipset and mainboard
45 * dependent and should be updated accordingly.
46 *
47 * These values are used by the PCI configuration space,
48 * MP Tables. TODO: Make ACPI use these values too.
49 */
50static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
Piotr Króldcd2f172016-05-27 12:04:13 +020051 [0 ... FCH_INT_TABLE_SIZE-1] = 0x1F,
Piotr Króldcd2f172016-05-27 12:04:13 +020052 /* INTA# - INTH# */
53 [0x00] = 0x03,0x03,0x05,0x07,0x0B,0x0A,0x1F,0x1F,
54 /* Misc-nil,0,1,2, INT from Serial irq */
55 [0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
56 /* SCI, SMBUS0, ASF, HDA, FC, RSVD, PerMon, SD */
57 [0x10] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
58 [0x18] = 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
59 /* IMC INT0 - 5 */
60 [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,
61 [0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
62 /* USB Devs 18/19/22 INTA-C */
63 [0x30] = 0x05,0x1F,0x05,0x1F,0x04,0x1F,0x1F,0x1F,
64 [0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
65 /* SATA */
66 [0x40] = 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,
67 [0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
68 [0x50] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
69 [0x58] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
70 [0x60] = 0x00,0x00,0x1F
71};
72
73static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
Piotr Króldcd2f172016-05-27 12:04:13 +020074 [0 ... FCH_INT_TABLE_SIZE-1] = 0x1F,
Piotr Króldcd2f172016-05-27 12:04:13 +020075 /* INTA# - INTH# */
76 [0x00] = 0x10,0x10,0x12,0x13,0x14,0x15,0x1F,0x1F,
77 /* Misc-nil,0,1,2, INT from Serial irq */
78 [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
79 /* SCI, SMBUS0, ASF, HDA, FC, RSVD, PerMon, SD */
80 [0x10] = 0x09,0x1F,0x1F,0x1F,0x1F,0x1f,0x1F,0x10,
81 [0x18] = 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
82 /* IMC INT0 - 5 */
83 [0x20] = 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,
84 [0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
85 /* USB Devs 18/19/20/22 INTA-C */
86 [0x30] = 0x12,0x1f,0x12,0x1F,0x12,0x1F,0x1F,0x00,
87 [0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
88 /* SATA */
89 [0x40] = 0x1f,0x13,0x00,0x00,0x00,0x00,0x00,0x00,
90 [0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
91 [0x50] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
92 [0x58] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
93 [0x60] = 0x00,0x00,0x1F
94};
95
96/*
97 * This table defines the index into the picr/intr_data
98 * tables for each device. Any enabled device and slot
99 * that uses hardware interrupts should have an entry
100 * in this table to define its index into the FCH
101 * PCI_INTR register 0xC00/0xC01. This index will define
102 * the interrupt that it should use. Putting PIRQ_A into
103 * the PIN A index for a device will tell that device to
104 * use PIC IRQ 10 if it uses PIN A for its hardware INT.
105 */
106static const struct pirq_struct mainboard_pirq_data[] = {
107 /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */
108 {GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */
109 {ACTL_DEVFN,{PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* Audio: 01.1 */
110 {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* x4 PCIe: 02.1 */
111 {NB_PCIE_PORT2_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* mPCIe: 02.2 */
112 {NB_PCIE_PORT3_DEVFN, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B}}, /* NIC: 02.3 */
113 {XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* XHCI: 10.0 */
114 {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */
115 {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */
116 {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */
117 {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */
118 {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */
119 {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */
120 {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */
121 {SD_DEVFN, {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SD: 14.7 */
122 {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 (same device as xHCI 10.0) */
123 {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 (same device as xHCI 10.1) */
124};
125
126/* PIRQ Setup */
127static void pirq_setup(void)
128{
129 pirq_data_ptr = mainboard_pirq_data;
130 pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct);
131 intr_data_ptr = mainboard_intr_data;
132 picr_data_ptr = mainboard_picr_data;
133}
134
135/* Wrapper to enable GPIO/UART devices under menuconfig. Revisit
136 * once configuration file format for SPI flash storage is complete.
137 */
138#define SIO_PORT 0x2e
139
140static void config_gpio_mux(void)
141{
142 struct device *uart, *gpio;
143
144 uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3);
145 gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO0);
146 if (uart)
147 uart->enabled = CONFIG_APU2_PINMUX_UART_C;
148 if (gpio)
149 gpio->enabled = CONFIG_APU2_PINMUX_GPIO0;
150
151 uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4);
152 gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO1);
153 if (uart)
154 uart->enabled = CONFIG_APU2_PINMUX_UART_D;
155 if (gpio)
156 gpio->enabled = CONFIG_APU2_PINMUX_GPIO1;
157}
158
159/**********************************************
160 * enable the dedicated function in mainboard.
161 **********************************************/
162
163static void mainboard_enable(device_t dev)
164{
165 printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
166
167 config_gpio_mux();
168
169 //
170 // Enable the RTC output
171 //
172 pm_write16 ( PM_RTC_CONTROL, pm_read16( PM_RTC_CONTROL ) | (1 << 11));
173
174 //
175 // Enable power on from WAKE#
176 //
177 pm_write16 ( PM_S_STATE_CONTROL, pm_read16( PM_S_STATE_CONTROL ) | (1 << 14));
178
Piotr Króldcd2f172016-05-27 12:04:13 +0200179 /* Initialize the PIRQ data structures for consumption */
180 pirq_setup();
181}
182
Kyösti Mälkki10407492017-01-16 19:59:52 +0200183/*
Kyösti Mälkki01bf5992017-01-16 19:50:28 +0200184 * We will stuff a modified version of the first NICs (BDF 1:0.0) MAC address
185 * into the smbios serial number location.
186 */
187const char *smbios_mainboard_serial_number(void)
188{
189 static char serial[10];
190 device_t nic_dev;
191 uintptr_t bar10;
192 u32 mac_addr = 0;
193 int i;
194
195 nic_dev = dev_find_slot(1, PCI_DEVFN(0, 0));
196 if ((serial[0] != 0) || !nic_dev)
197 return serial;
198
199 /* Read in the last 3 bytes of NIC's MAC address. */
200 bar10 = pci_read_config32(nic_dev, 0x10);
201 bar10 &= 0xFFFE0000;
202 bar10 += 0x5400;
203 for (i = 3; i < 6; i++) {
204 mac_addr <<= 8;
205 mac_addr |= read8((u8 *)bar10 + i);
206 }
207 mac_addr &= 0x00FFFFFF;
208 mac_addr /= 4;
209 mac_addr -= 64;
210
211 snprintf(serial, sizeof(serial), "%d", mac_addr);
212 return serial;
213}
214
215/*
Kyösti Mälkki10407492017-01-16 19:59:52 +0200216 * We will stuff the memory size into the smbios sku location.
217 */
218const char *smbios_mainboard_sku(void)
219{
220 static char sku[5];
221 if (sku[0] != 0)
222 return sku;
223
224 if (!get_spd_offset())
225 snprintf(sku, sizeof(sku), "2 GB");
226 else
227 snprintf(sku, sizeof(sku), "4 GB");
228 return sku;
229}
230
Piotr Króldcd2f172016-05-27 12:04:13 +0200231struct chip_operations mainboard_ops = {
232 .enable_dev = mainboard_enable,
233};