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review.coreboot.org / coreboot / 467a87abcea13a1b0b61223a175cf46b16474965 / . / src / mainboard / intel / kblrvp / variants / rvp7 / include / variant / gpio.h
blob: 2233339bc10a63b3e91f8e47f3bd2acc7acfa894 [file] [log] [blame]
Barnali Sarkar2ed14f62016-11-29 16:51:08 +0530[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2013 Google Inc.
5 * Copyright (C) 2015 Intel Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
14 * GNU General Public License for more details.
15 */
16
17#ifndef _GPIORVP7_H
18#define _GPIORVP7_H
19
20#include <soc/gpe.h>
21#include <soc/gpio.h>
22
23/* TCA6424A I/O Expander */
24#define IO_EXPANDER_BUS 4
25#define IO_EXPANDER_0_ADDR 0x22
26#define IO_EXPANDER_P0CONF 0x0C /* Port 0 conf offset */
27#define IO_EXPANDER_P0DOUT 0x04 /* Port 0 data offset */
28#define IO_EXPANDER_P1CONF 0x0D
29#define IO_EXPANDER_P1DOUT 0x05
30#define IO_EXPANDER_P2CONF 0x0E
31#define IO_EXPANDER_P2DOUT 0x06
32#define IO_EXPANDER_1_ADDR 0x23
33
34
35/* GPE_EC_WAKE */
36#define GPE_EC_WAKE GPE0_LAN_WAK
37
38/* CHROMEEC in RVP */
39#define EC_SCI_GPI GPP_E16
40#define EC_SMI_GPI GPP_E15
41/*
42 * Gpio based irq for touchpad, 18th index in North Bank
43 * MAX_DIRECT_IRQ + GPSW_SIZE + 19
44 */
45#define KBLRVP_TOUCHPAD_IRQ 33
46
47#define KBLRVP_TOUCH_IRQ 31
48
49#define BOARD_TOUCHPAD_NAME "touchpad"
50#define BOARD_TOUCHPAD_IRQ KBLRVP_TOUCHPAD_IRQ
51#define BOARD_TOUCHPAD_I2C_BUS 0
52#define BOARD_TOUCHPAD_I2C_ADDR 0x20
53
54#define BOARD_TOUCHSCREEN_NAME "touchscreen"
55#define BOARD_TOUCHSCREEN_IRQ KBLRVP_TOUCH_IRQ
56#define BOARD_TOUCHSCREEN_I2C_BUS 0
57#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4c
58
59#ifndef __ACPI__
60
61/* Pad configuration in ramstage. */
62static const struct pad_config gpio_table[] = {
63/* PM_SLP_S0ix_R_N*/ PAD_CFG_GPO(GPP_A7, 1, DEEP),
64/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
65/* PCH_CLK_PCI_TPM */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
66/* PCH_LPC_CLK */ PAD_CFG_GPI_APIC(GPP_A11, NONE, DEEP),
67/* ISH_KB_PROX_INT */ PAD_CFG_GPO(GPP_A12, 1, RSMRST),
68/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
69/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1),
70/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
71/* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
72/* ACCEL INTERRUPT */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
73/* ISH_GP1 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
74/* GYRO_DRDY */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
75/* FLIP_ACCEL_INT */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),
76/* GYRO_INT */ PAD_CFG_GPO(GPP_A22, 1, DEEP),
77/* ISH_GP5 */ PAD_CFG_GPI_APIC(GPP_A23, NONE, DEEP),
78/* CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
79/* CORE_VID1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
80/* HSJ_MIC_DET */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
81/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST),
82/* BT_RF_KILL */ PAD_CFG_GPO(GPP_B4, 1, DEEP),
83/* SRCCLKREQ0# */ PAD_CFG_GPI_APIC(GPP_B5, NONE, DEEP),
84/* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
85/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
86/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
87/* GPP_B_14_SPKR */ PAD_CFG_TERM_GPO(GPP_B14, 1, 20K_PD, DEEP),
88/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, PLTRST, YES),
89/* TBT_CIO_PLUG_EVT */ PAD_CFG_GPI_ACPI_SCI(GPP_B17, 20K_PU, PLTRST, YES),
90/* PCH_SLOT1_WAKE_N */ PAD_CFG_GPI_ACPI_SCI(GPP_B18, 20K_PU, PLTRST, YES),
91/* CCODEC_SPI_CS */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
92/* CODEC_SPI_CLK */ PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1),
93/* CODEC_SPI_MISO */ PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1),
94/* CODEC_SPI_MOSI */ PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1),
95/* SM1ALERT# */ PAD_CFG_TERM_GPO(GPP_B23, 1, 20K_PD, DEEP),
96/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
97/* SMB_DATA */ PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1),
98/* SMBALERT# */ PAD_CFG_TERM_GPO(GPP_C2, 1, 20K_PD, DEEP),
99/* M2_WWAN_PWREN */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
100/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
101/* SML0ALERT# */ PAD_CFG_GPI_APIC(GPP_C5, 20K_PD, DEEP),
102/* EC_IN_RW */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
103/* USB_CTL */ PAD_CFG_NF(GPP_C7, 20K_PD, DEEP, NF1),
104/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
105/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
106/* NFC_RST* */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
107/* EN_PP3300_KEPLER */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
108/* PCH_MEM_CFG0 */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
109/* PCH_MEM_CFG1 */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
110/* PCH_MEM_CFG2 */ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
111/* PCH_MEM_CFG3 */ PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1),
112/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
113/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
114/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
115/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
116/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
117/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
118/* TCH_PNL_PWREN */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
119/* SPI_WP_STATUS */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
120/* ITCH_SPI_CS */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1),
121/* ITCH_SPI_CLK */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),
122/* ITCH_SPI_MISO_1 */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1),
123/* ITCH_SPI_MISO_0 */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1),
124/* CAM_FLASH_STROBE */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
125/* EN_PP3300_DX_EMMC */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
126/* EN_PP1800_DX_EMMC */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
127/* SH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
128/* SH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
129 PAD_CFG_GPI(GPP_D9, NONE, DEEP),
130/* SD_D3_WAKE */ PAD_CFG_GPI(GPP_D10, NONE, DEEP),
131/* USB_A1_ILIM_SEL */ PAD_CFG_GPI(GPP_D11, NONE, DEEP),
132/* EN_PP3300_DX_CAM */ PAD_CFG_GPI(GPP_D12, NONE, DEEP),
133/* EN_PP1800_DX_AUDIO */PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
134/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
135/* ISH_UART0_RTS */ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1),
136/* ISH_UART0_CTS */ PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
137/* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
138/* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, 20K_PD, DEEP, NF1),
139/* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
140/* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, 20K_PD, DEEP, NF1),
141/* ITCH_SPI_D2 */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
142/* ITCH_SPI_D3 */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
143/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
144/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, 20K_PD, DEEP),
145/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
146/* SSD_PEDET */ PAD_CFG_GPI(GPP_E2, NONE, DEEP),
147/* CPU_GP0 */ PAD_CFG_GPO(GPP_E3, 1, RSMRST),
148/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
149/* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1),
150 PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
151/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
152/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
153/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
154/* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
155/* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
156/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES),
157/* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, PLTRST, YES),
158/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
159/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
160/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1),
161/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
162/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
163/* PCH_CODEC_IRQ */ PAD_CFG_GPI_APIC(GPP_E22, NONE, DEEP),
164/* TCH_PNL_RST */ PAD_CFG_TERM_GPO(GPP_E23, 1, 20K_PD, DEEP),
165/* I2S2_SCLK */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
166/* I2S2_SFRM */ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),
167/* I2S2_TXD */ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
168/* I2S2_RXD */ PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1),
169/* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
170/* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1),
171/* I2C3_SDA */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
172/* I2C3_SCL */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1),
173/* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
174/* I2C4_SDA */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
175/* AUDIO_IRQ */ PAD_CFG_NF(GPP_F10, NONE, DEEP, NF2),
176/* I2C5_SCL */ PAD_CFG_NF(GPP_F11, NONE, DEEP, NF2),
177/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
178/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
179/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
180/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
181/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
182/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
183/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
184/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
185/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
186/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
187/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
188/* WWAN_UIM_SIM_DET */ PAD_CFG_GPI_APIC(GPP_F23, NONE, DEEP),
189/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
190/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
191/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
192/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
193/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
194/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
195/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
196/* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1),
197/* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
198/* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
199/* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
200/* EC_PCH_PWRBTN */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1),
201/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
202/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
203/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
204 PAD_CFG_NF(GPD7, NONE, DEEP, NF1),
205/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
206/* PCH_SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
207/* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
208/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
209};
210
211/* Early pad configuration in romstage. */
212static const struct pad_config early_gpio_table[] = {
213/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
214/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
215};
216
217
218#endif
219
220#endif