Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 7e61e45 | 2008-01-18 10:35:56 +0000 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2007 AMD |
| 5 | * Written by Yinghai Lu <yinghailu@amd.com> for AMD. |
| 6 | * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) |
| 7 | * Written by Morgan Tsai <my_tsai@sis.com> for SiS. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
Paul Menzel | a46a712 | 2013-02-23 18:37:27 +0100 | [diff] [blame] | 21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 22 | */ |
| 23 | |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 24 | #include <stdint.h> |
Patrick Georgi | 12aba82 | 2009-04-30 07:07:22 +0000 | [diff] [blame] | 25 | #include <string.h> |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 26 | #include <device/pci_def.h> |
| 27 | #include <device/pci_ids.h> |
| 28 | #include <arch/io.h> |
| 29 | #include <device/pnp_def.h> |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 30 | #include <cpu/x86/lapic.h> |
Edwin Beasant | eb50c7d | 2010-07-06 21:05:04 +0000 | [diff] [blame] | 31 | #include <pc80/mc146818rtc.h> |
Patrick Georgi | 12584e2 | 2010-05-08 09:14:51 +0000 | [diff] [blame] | 32 | #include <console/console.h> |
Uwe Hermann | 6dc92f0 | 2010-11-21 11:36:03 +0000 | [diff] [blame] | 33 | #include <spd.h> |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 34 | #include <cpu/amd/model_fxx_rev.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 35 | #include <southbridge/sis/sis966/sis966.h> |
stepan | 836ae29 | 2010-12-08 05:42:47 +0000 | [diff] [blame] | 36 | #include "southbridge/sis/sis966/early_smbus.c" |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 37 | #include <northbridge/amd/amdk8/raminit.h> |
Edward O'Callaghan | ebe3a7a | 2015-01-05 00:27:54 +1100 | [diff] [blame] | 38 | #include <delay.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 39 | #include <cpu/x86/lapic.h> |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 40 | #include "northbridge/amd/amdk8/reset_test.c" |
Edward O'Callaghan | f292002 | 2014-04-27 00:41:50 +1000 | [diff] [blame] | 41 | #include <superio/ite/common/ite.h> |
Edward O'Callaghan | 5c41ee6 | 2014-04-23 01:43:38 +1000 | [diff] [blame] | 42 | #include <superio/ite/it8716f/it8716f.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 43 | #include <cpu/x86/bist.h> |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 44 | #include "northbridge/amd/amdk8/debug.c" |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 45 | #include "northbridge/amd/amdk8/setup_resource_map.c" |
stepan | 836ae29 | 2010-12-08 05:42:47 +0000 | [diff] [blame] | 46 | #include "southbridge/sis/sis966/early_ctrl.c" |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 47 | |
Morgan Tsai | 218c265 | 2007-11-02 16:09:58 +0000 | [diff] [blame] | 48 | #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) |
Edward O'Callaghan | 5c41ee6 | 2014-04-23 01:43:38 +1000 | [diff] [blame] | 49 | #define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO) |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 50 | |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 51 | static void memreset(int controllers, const struct mem_controller *ctrl) { } |
| 52 | static void activate_spd_rom(const struct mem_controller *ctrl) { } |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 53 | |
| 54 | static inline int spd_read_byte(unsigned device, unsigned address) |
| 55 | { |
| 56 | return smbus_read_byte(device, address); |
| 57 | } |
| 58 | |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 59 | #include <northbridge/amd/amdk8/f.h> |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 60 | #include "northbridge/amd/amdk8/incoherent_ht.c" |
Stefan Reinauer | 23836e2 | 2010-04-15 12:39:29 +0000 | [diff] [blame] | 61 | #include "northbridge/amd/amdk8/coherent_ht.c" |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 62 | #include "northbridge/amd/amdk8/raminit_f.c" |
Stefan Reinauer | c13093b | 2009-09-23 18:51:03 +0000 | [diff] [blame] | 63 | #include "lib/generic_sdram.c" |
Morgan Tsai | 218c265 | 2007-11-02 16:09:58 +0000 | [diff] [blame] | 64 | #include "resourcemap.c" |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 65 | #include "cpu/amd/dualcore/dualcore.c" |
| 66 | |
| 67 | #define SIS966_NUM 1 |
| 68 | #define SIS966_USE_NIC 1 |
| 69 | #define SIS966_USE_AZA 1 |
| 70 | |
| 71 | #define SIS966_PCI_E_X_0 0 |
| 72 | |
| 73 | #define SIS966_MB_SETUP \ |
| 74 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \ |
| 75 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \ |
| 76 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \ |
| 77 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \ |
| 78 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ |
| 79 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ |
| 80 | |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 81 | #include <southbridge/sis/sis966/early_setup_ss.h> |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 82 | #include "cpu/amd/model_fxx/init_cpus.c" |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 83 | #include "cpu/amd/model_fxx/fidvid.c" |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 84 | #include "northbridge/amd/amdk8/early_ht.c" |
| 85 | |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 86 | static void sio_setup(void) |
| 87 | { |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 88 | uint32_t dword; |
| 89 | uint8_t byte; |
| 90 | |
| 91 | byte = pci_read_config8(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0x7b); |
Morgan Tsai | 218c265 | 2007-11-02 16:09:58 +0000 | [diff] [blame] | 92 | byte |= 0x20; |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 93 | pci_write_config8(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0x7b, byte); |
Morgan Tsai | 218c265 | 2007-11-02 16:09:58 +0000 | [diff] [blame] | 94 | |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 95 | dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa0); |
| 96 | dword |= (1<<0); |
| 97 | pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa0, dword); |
Morgan Tsai | 218c265 | 2007-11-02 16:09:58 +0000 | [diff] [blame] | 98 | |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 99 | dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4); |
| 100 | dword |= (1<<16); |
| 101 | pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4, dword); |
| 102 | } |
| 103 | |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 104 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 105 | { |
| 106 | static const uint16_t spd_addr [] = { |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 107 | // Node 0 |
| 108 | DIMM0, DIMM2, 0, 0, |
| 109 | DIMM1, DIMM3, 0, 0, |
| 110 | // Node 1 |
| 111 | DIMM4, DIMM6, 0, 0, |
| 112 | DIMM5, DIMM7, 0, 0, |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 113 | }; |
| 114 | |
Patrick Georgi | bbc880e | 2012-11-20 18:20:56 +0100 | [diff] [blame] | 115 | struct sys_info *sysinfo = &sysinfo_car; |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 116 | int needs_reset = 0; |
| 117 | unsigned bsp_apicid = 0; |
| 118 | |
Patrick Georgi | 2bd9100 | 2010-03-18 16:46:50 +0000 | [diff] [blame] | 119 | if (!cpu_init_detectedx && boot_cpu()) { |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 120 | /* Nothing special needs to be done to find bus 0 */ |
| 121 | /* Allow the HT devices to be found */ |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 122 | enumerate_ht_chain(); |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 123 | sio_setup(); |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 124 | } |
| 125 | |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 126 | if (bist == 0) |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 127 | bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 128 | |
Edward O'Callaghan | f292002 | 2014-04-27 00:41:50 +1000 | [diff] [blame] | 129 | ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48); |
| 130 | ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 131 | |
| 132 | setup_mb_resource_map(); |
| 133 | |
Stefan Reinauer | 42fa7fe | 2011-04-20 20:54:07 +0000 | [diff] [blame] | 134 | console_init(); |
Morgan Tsai | 218c265 | 2007-11-02 16:09:58 +0000 | [diff] [blame] | 135 | |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 136 | /* Halt if there was a built in self test failure */ |
| 137 | report_bist_failure(bist); |
| 138 | |
Myles Watson | 08e0fb8 | 2010-03-22 16:33:25 +0000 | [diff] [blame] | 139 | printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 140 | |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 141 | printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 142 | |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 143 | set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 144 | setup_coherent_ht_domain(); // routing table and start other core0 |
| 145 | |
| 146 | wait_all_core0_started(); |
Patrick Georgi | e166782 | 2012-05-05 15:29:32 +0200 | [diff] [blame] | 147 | #if CONFIG_LOGICAL_CPUS |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 148 | // It is said that we should start core1 after all core0 launched |
| 149 | /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, |
| 150 | * So here need to make sure last core0 is started, esp for two way system, |
| 151 | * (there may be apic id conflicts in that case) |
| 152 | */ |
| 153 | start_other_cores(); |
| 154 | wait_all_other_cores_started(bsp_apicid); |
| 155 | #endif |
| 156 | |
| 157 | /* it will set up chains and store link pair for optimization later */ |
| 158 | ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn |
| 159 | |
Patrick Georgi | 76e8152 | 2010-11-16 21:25:29 +0000 | [diff] [blame] | 160 | #if CONFIG_SET_FIDVID |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 161 | { |
| 162 | msr_t msr; |
| 163 | msr=rdmsr(0xc0010042); |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 164 | printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 165 | } |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 166 | enable_fid_change(); |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 167 | enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 168 | init_fidvid_bsp(bsp_apicid); |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 169 | // show final fid and vid |
| 170 | { |
| 171 | msr_t msr; |
| 172 | msr=rdmsr(0xc0010042); |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 173 | printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 174 | } |
| 175 | #endif |
| 176 | |
| 177 | needs_reset |= optimize_link_coherent_ht(); |
| 178 | needs_reset |= optimize_link_incoherent_ht(sysinfo); |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 179 | |
| 180 | // fidvid change will issue one LDTSTOP and the HT change will be effective too |
| 181 | if (needs_reset) { |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 182 | printk(BIOS_INFO, "ht reset -\n"); |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 183 | soft_reset(); |
| 184 | } |
| 185 | allow_all_aps_stop(bsp_apicid); |
| 186 | |
| 187 | //It's the time to set ctrl in sysinfo now; |
| 188 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); |
| 189 | |
| 190 | sis_init_stage1(); |
Morgan Tsai | 218c265 | 2007-11-02 16:09:58 +0000 | [diff] [blame] | 191 | enable_smbus(); |
| 192 | |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 193 | //do we need apci timer, tsc...., only debug need it for better output |
| 194 | /* all ap stopped? */ |
Paul Menzel | 4549e5a | 2014-02-02 22:05:48 +0100 | [diff] [blame^] | 195 | // init_timer(); // Need to use TMICT to synchronize FID/VID |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 196 | |
| 197 | sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); |
| 198 | |
| 199 | sis_init_stage2(); |
| 200 | post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now |
Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame] | 201 | } |