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Damien Zammit62477932015-05-03 21:34:38 +10001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#ifndef NORTHBRIDGE_INTEL_PINEVIEW_H
18#define NORTHBRIDGE_INTEL_PINEVIEW_H
19
20#include <northbridge/intel/pineview/iomap.h>
21#include <southbridge/intel/i82801gx/i82801gx.h>
22
Damien Zammitf7060f12015-11-14 00:59:21 +110023#define BOOT_PATH_NORMAL 0
24#define BOOT_PATH_RESET 1
25#define BOOT_PATH_RESUME 2
26
27#define SYSINFO_DIMM_NOT_POPULATED 0x00
28#define SYSINFO_DIMM_X16SS 0x01
29#define SYSINFO_DIMM_X16DS 0x02
30#define SYSINFO_DIMM_X8DS 0x05
31#define SYSINFO_DIMM_X8DDS 0x06
32
Damien Zammit62477932015-05-03 21:34:38 +100033/* Device 0:0.0 PCI configuration space (Host Bridge) */
34
35#define EPBAR 0x40
36#define MCHBAR 0x48
37#define PCIEXBAR 0x60
38#define DMIBAR 0x68
39#define PMIOBAR 0x78
40
41#define GGC 0x52 /* GMCH Graphics Control */
42
43#define DEVEN 0x54 /* Device Enable */
44#define DEVEN_D0F0 (1 << 0)
45#define DEVEN_D1F0 (1 << 1)
46#define DEVEN_D2F0 (1 << 3)
47#define DEVEN_D2F1 (1 << 4)
48
49#ifndef BOARD_DEVEN
50#define BOARD_DEVEN ( DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1 )
51#endif /* BOARD_DEVEN */
52
53#define PAM0 0x90
54#define PAM1 0x91
55#define PAM2 0x92
56#define PAM3 0x93
57#define PAM4 0x94
58#define PAM5 0x95
59#define PAM6 0x96
60
61#define LAC 0x97 /* Legacy Access Control */
62#define REMAPBASE 0x98
63#define REMAPLIMIT 0x9a
64#define SMRAM 0x9d /* System Management RAM Control */
Arthur Heymans4bdfebd2018-04-09 22:10:33 +020065#define ESMRAMC 0x9e /* Extended System Management RAM Control */
Damien Zammit62477932015-05-03 21:34:38 +100066
67#define TOM 0xa0
68#define TOUUD 0xa2
69#define GBSM 0xa4
70#define BGSM 0xa8
Damien Zammitf7060f12015-11-14 00:59:21 +110071#define TSEG 0xac
Damien Zammit62477932015-05-03 21:34:38 +100072#define TOLUD 0xb0 /* Top of Low Used Memory */
73#define ERRSTS 0xc8
74#define ERRCMD 0xca
75#define SMICMD 0xcc
76#define SCICMD 0xce
77#define CGDIS 0xd8
78#define SKPAD 0xdc /* Scratchpad Data */
79#define CAPID0 0xe0
80#define DEV0T 0xf0
81#define MSLCK 0xf4
82#define MID0 0xf8
83#define DEBUP0 0xfc
84
85/* Device 0:1.0 PCI configuration space (PCI Express) */
86
87#define BCTRL1 0x3e /* 16bit */
88#define PEGSTS 0x214 /* 32bit */
89
Damien Zammit62477932015-05-03 21:34:38 +100090/* Device 0:2.0 PCI configuration space (Graphics Device) */
91
92#define GMADR 0x18
93#define GTTADR 0x1c
94#define BSM 0x5c
Damien Zammit62477932015-05-03 21:34:38 +100095
Damien Zammitf7060f12015-11-14 00:59:21 +110096#define GPIO32(x) *((volatile u32 *)(DEFAULT_GPIOBASE + x))
Damien Zammit62477932015-05-03 21:34:38 +100097
98/*
99 * MCHBAR
100 */
101
102#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x))
103#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x))
104#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x))
105
106/*
107 * EPBAR - Egress Port Root Complex Register Block
108 */
109
110#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x))
111#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x))
112#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x))
113
114/*
115 * DMIBAR
116 */
117
118#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x))
119#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x))
120#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x))
121
Damien Zammitf7060f12015-11-14 00:59:21 +1100122enum fsb_clk {
123 FSB_CLOCK_667MHz = 0,
124 FSB_CLOCK_800MHz = 1,
125};
126
127enum mem_clk {
128 MEM_CLOCK_667MHz = 0,
129 MEM_CLOCK_800MHz = 1,
130};
131
132enum ddr {
133 DDR2 = 2,
134 DDR3 = 3,
135};
136
137enum chip_width { /* as in DDR3 spd */
138 CHIP_WIDTH_x4 = 0,
139 CHIP_WIDTH_x8 = 1,
140 CHIP_WIDTH_x16 = 2,
141 CHIP_WIDTH_x32 = 3,
142};
143
144enum chip_cap { /* as in DDR3 spd */
145 CHIP_CAP_256M = 0,
146 CHIP_CAP_512M = 1,
147 CHIP_CAP_1G = 2,
148 CHIP_CAP_2G = 3,
149 CHIP_CAP_4G = 4,
150 CHIP_CAP_8G = 5,
151 CHIP_CAP_16G = 6,
152};
153
154struct timings {
155 unsigned int CAS;
156 enum fsb_clk fsb_clock;
157 enum mem_clk mem_clock;
158 unsigned int tRAS;
159 unsigned int tRP;
160 unsigned int tRCD;
161 unsigned int tWR;
162 unsigned int tRFC;
163 unsigned int tWTR;
164 unsigned int tRRD;
165 unsigned int tRTP;
166};
167
168struct dimminfo {
169 unsigned int card_type; /* 0x0: unpopulated,
170 0xa - 0xf: raw card type A - F */
171 u8 type;
172 enum chip_width width;
173 enum chip_cap chip_capacity;
174 unsigned int page_size; /* of whole DIMM in Bytes (4096 or 8192) */
175 unsigned int sides;
176 unsigned int banks;
177 unsigned int ranks;
178 unsigned int rows;
179 unsigned int cols;
180 unsigned int cas_latencies;
181 unsigned int tAAmin;
182 unsigned int tCKmin;
183 unsigned int tWR;
184 unsigned int tRP;
185 unsigned int tRCD;
186 unsigned int tRAS;
Martin Roth128c1042016-11-18 09:29:03 -0700187 unsigned int rank_capacity_mb; /* per rank in Megabytes */
Damien Zammitf7060f12015-11-14 00:59:21 +1100188 u8 spd_data[256];
189};
190
191struct pllparam {
192 u8 kcoarse[2][72];
193 u8 pi[2][72];
194 u8 dben[2][72];
195 u8 dbsel[2][72];
196 u8 clkdelay[2][72];
197};
198
199struct sysinfo {
200 u8 maxpi;
201 u8 pioffset;
202 u8 pi[8];
203 u16 coarsectrl;
204 u16 coarsedelay;
205 u16 mediumphase;
206 u16 readptrdelay;
207
208 int txt_enabled;
209 int cores;
210 int boot_path;
211 int max_ddr2_mhz;
212 int max_ddr3_mt;
213 int max_fsb_mhz;
214 int max_render_mhz;
215 int enable_igd;
216 int enable_peg;
217 u16 ggc;
218
219 int dimm_config[2];
220 int dimms_per_ch;
221 int spd_type;
222 int channel_capacity[2];
223 struct timings selected_timings;
224 struct dimminfo dimms[4];
225 u8 spd_map[4];
226
227 u8 nodll;
228 u8 async;
229 u8 dt0mode;
230 u8 mvco4x; /* 0 (8x) or 1 (4x) */
231};
232
233void pineview_early_initialization(void);
234u32 decode_igd_memory_size(const u32 gms);
235u32 decode_igd_gtt_size(const u32 gsm);
236u8 decode_pciebar(u32 *const base, u32 *const len);
237
Arthur Heymansc6ff1ac2019-01-11 16:06:19 +0100238/* Mainboard romstage callback functions */
239void mb_enable_lpc(void);
240void get_mb_spd_addrmap(u8 *spd_addr_map);
241void mb_pirq_setup(void); /* optional */
242
Damien Zammitf7060f12015-11-14 00:59:21 +1100243struct acpi_rsdp;
244unsigned long northbridge_write_acpi_tables(unsigned long start, struct acpi_rsdp *rsdp);
245
Damien Zammit62477932015-05-03 21:34:38 +1000246#endif /* NORTHBRIDGE_INTEL_PINEVIEW_H */