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Martin Roth58562402015-10-11 10:36:26 +02001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2011 Google Inc.
5 * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Martin Roth58562402015-10-11 10:36:26 +020015 */
16
Martin Roth58562402015-10-11 10:36:26 +020017#include <cbmem.h>
18#include <device/pci_def.h>
Martin Roth58562402015-10-11 10:36:26 +020019#include <drivers/intel/fsp1_0/fsp_util.h>
20
Elyes HAOUASa1e22b82019-03-18 22:49:36 +010021#include "northbridge.h"
22
Martin Roth58562402015-10-11 10:36:26 +020023static uintptr_t smm_region_start(void)
24{
25 /*
26 * Calculate the top of usable (low) DRAM.
27 * The FSP's reserved memory sits just below the SMM region,
28 * allowing calculation of the top of usable memory.
29 */
30 uintptr_t tom = sideband_read(B_UNIT, BMBOUND);
31 uintptr_t bsmmrrl = sideband_read(B_UNIT, BSMMRRL) << 20;
32 if (bsmmrrl) {
33 tom = bsmmrrl;
34 }
35
36 return tom;
37}
38
39void *cbmem_top(void)
40{
41 return (void *) (smm_region_start() - FSP_RESERVE_MEMORY_SIZE);
42}