blob: 75d1bb2b05348f718be892ec0743db60b6e1be98 [file] [log] [blame]
Martin Roth58562402015-10-11 10:36:26 +02001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2009-2010 iWave Systems
5 * Copyright (C) 2013 Sage Electronic Engineering, LLC.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Martin Roth58562402015-10-11 10:36:26 +020015 */
16
Kyösti Mälkki5efddd72016-12-07 14:32:18 +020017#define __SIMPLE_DEVICE__
Martin Roth58562402015-10-11 10:36:26 +020018
19#include <stdint.h>
Kyösti Mälkkif1b58b72019-03-01 13:43:02 +020020#include <device/pci_ops.h>
Martin Roth58562402015-10-11 10:36:26 +020021#include <device/pci_def.h>
Martin Roth58562402015-10-11 10:36:26 +020022#include <cpu/x86/lapic.h>
23#include "northbridge.h"
24
25/*
26 * Restricted Access Regions:
27 *
28 * MCR - Message Control Register
29 * 31 24 16 8 4 0
30 * ----------------------------------------------------------------------------
31 * | | | Target | Write | |
32 * | Opcode | Port | register | byte | Reserved |
33 * | | | Address | Enables | |
34 * ----------------------------------------------------------------------------
35 *
36 * MDR - Message Data Register
37 * 31 0
38 * ----------------------------------------------------------------------------
39 * | |
40 * | Data |
41 * | |
42 * ----------------------------------------------------------------------------
43 */
44
Elyes HAOUAS106e2852017-06-17 12:06:45 +020045#define MSG_OPCODE_READ (0x10 << 24)
46#define MSG_OPCODE_WRITE (0x11 << 24)
Martin Roth58562402015-10-11 10:36:26 +020047
48#define MCR 0xD0
49#define MDR 0xD4
50#define MCRE 0xD8
51
52u32 sideband_read(int port, int reg)
53{
54 pci_write_config32(PCI_DEV(0, 0, 0), MCR,
55 (MSG_OPCODE_READ | (port << 16) | (reg << 8)));
56 return pci_read_config32(PCI_DEV(0, 0, 0), MDR);
57}
58
59void sideband_write(int port, int reg, long data)
60{
61 pci_write_config32(PCI_DEV(0, 0, 0), MDR, data);
62 pci_write_config32(PCI_DEV(0, 0, 0), MCR,
63 (MSG_OPCODE_WRITE | (port << 16) | (reg << 8) | (0xF << 4)));
64 pci_read_config32(PCI_DEV(0, 0, 0), MDR);
65}