blob: 160d75477a8c1d422e54beb3725de1f9267ace1f [file] [log] [blame]
Martin Roth58562402015-10-11 10:36:26 +02001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2008 coresystems GmbH
5 * Copyright (C) 2011 Google Inc.
6 * Copyright (C) 2013 Sage Electronic Engineering, LLC.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Martin Roth58562402015-10-11 10:36:26 +020016 */
17
18#ifndef __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__
19#define __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__
20
21#define DEFAULT_ECBASE CONFIG_MMCONF_BASE_ADDRESS
22
23/* Everything below this line is ignored in the DSDT */
24#ifndef __ACPI__
25
Martin Roth58562402015-10-11 10:36:26 +020026#include <device/device.h>
27
28/* Device 0:0.0 PCI configuration space (Host Bridge) */
29
30/* SideBand B-UNIT */
31#define B_UNIT 3
32 #define BNOCACHE 0x23
33 #define BNOCACHECTL 0x24
34 #define BMBOUND 0x25
35 #define BMBOUND_HI 0x26
36 #define BECREG 0x27
37 #define BMISC 0x28
38 #define BSMMRRL 0x2E
39 #define BSMMRRH 0x2F
40 #define BIMR0L 0x80
41 #define BIMR0H 0x81
42 #define BIMR0RAC 0x82
43 #define BIMR0WAC 0x83
44
45/* SideBand C-UNIT */
46#define C_UNIT 8
47
48/* SideBand D-UNIT */
49#define D_UNIT 1
50
51/* SideBand P-UNIT */
52#define P_UNIT 4
53
54#ifndef __ASSEMBLER__
55static inline void barrier(void) { asm("" ::: "memory"); }
56
57#define PCI_DEVICE_ID_RG_MIN 0x1F00
58#define PCI_DEVICE_ID_RG_MAX 0x1F0F
59#define SKPAD 0xFC
60
61int bridge_silicon_revision(void);
62void rangeley_late_initialization(void);
63u32 sideband_read(int port, int reg);
64void sideband_write(int port, int reg, long data);
65
Antonello Dettori305224f2016-09-03 10:45:33 +020066#ifndef __SIMPLE_DEVICE__
Elyes HAOUAS09d1d592018-02-09 08:38:14 +010067void northbridge_acpi_fill_ssdt_generator(struct device *device);
Martin Roth58562402015-10-11 10:36:26 +020068#endif
69
70#endif /* #ifndef __ASSEMBLER__ */
71#endif /* #ifndef __ACPI__ */
Martin Rothfd277d82016-01-11 12:47:30 -070072#endif /* __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__ */