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Yinghai Lu72ee9b02005-12-14 02:39:33 +00001/*
Stefan Reinauer1bfbbc02012-06-07 14:00:07 -07002 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2001 Eric Biederman
5 * Copyright (C) 2001 Ronald G. Minnich
6 * Copyright (C) 2005 Yinghai Lu
7 * Copyright (C) 2008 coresystems GmbH
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
Paul Menzela46a7122013-02-23 18:37:27 +010020 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Stefan Reinauer1bfbbc02012-06-07 14:00:07 -070021 */
Yinghai Lu72ee9b02005-12-14 02:39:33 +000022
Eric Biedermanfcd5ace2004-10-14 19:29:29 +000023#include <cpu/x86/lapic.h>
24#include <delay.h>
Stefan Reinauer75dbc382012-10-15 15:19:43 -070025#include <lib.h>
Eric Biedermanfcd5ace2004-10-14 19:29:29 +000026#include <string.h>
27#include <console/console.h>
28#include <arch/hlt.h>
29#include <device/device.h>
30#include <device/path.h>
31#include <smp/atomic.h>
32#include <smp/spinlock.h>
33#include <cpu/cpu.h>
Stefan Reinauer2bdfb482012-04-03 16:17:11 -070034#include <cpu/intel/speedstep.h>
Eric Biedermanfcd5ace2004-10-14 19:29:29 +000035
Ronald G. Minnich000bf832012-06-06 13:00:24 -070036#if CONFIG_SMP && CONFIG_MAX_CPUS > 1
Eric Biedermanfcd5ace2004-10-14 19:29:29 +000037/* This is a lot more paranoid now, since Linux can NOT handle
Zheng Baod4c5c442010-02-20 09:38:16 +000038 * being told there is a CPU when none exists. So any errors
39 * will return 0, meaning no CPU.
Eric Biedermanfcd5ace2004-10-14 19:29:29 +000040 *
41 * We actually handling that case by noting which cpus startup
42 * and not telling anyone about the ones that dont.
Zheng Baod4c5c442010-02-20 09:38:16 +000043 */
Kyösti Mälkki63539bb2012-07-05 06:31:15 +030044
45/* Start-UP IPI vector must be 4kB aligned and below 1MB. */
46#define AP_SIPI_VECTOR 0x1000
Yinghai Lu72ee9b02005-12-14 02:39:33 +000047
Patrick Georgie1667822012-05-05 15:29:32 +020048#if CONFIG_HAVE_ACPI_RESUME
Rudolf Mareka572f832009-04-13 17:57:44 +000049char *lowmem_backup;
50char *lowmem_backup_ptr;
51int lowmem_backup_size;
52#endif
53
Myles Watson6e235762009-09-29 14:56:15 +000054extern char _secondary_start[];
Aaron Durbina146d582013-02-08 16:56:51 -060055extern char _secondary_gdt_addr[];
56extern char gdt[];
57extern char gdt_end[];
58
59static inline void setup_secondary_gdt(void)
60{
61 u16 *gdt_limit;
62 u32 *gdt_base;
63
64 gdt_limit = (void *)&_secondary_gdt_addr;
65 gdt_base = (void *)&gdt_limit[1];
66
67 *gdt_limit = (u32)&gdt_end - (u32)&gdt - 1;
68 *gdt_base = (u32)&gdt;
69}
Myles Watson6e235762009-09-29 14:56:15 +000070
Stefan Reinauer1bfbbc02012-06-07 14:00:07 -070071static void copy_secondary_start_to_lowest_1M(void)
Yinghai Lu72ee9b02005-12-14 02:39:33 +000072{
Zheng Baod4c5c442010-02-20 09:38:16 +000073 extern char _secondary_start_end[];
74 unsigned long code_size;
Yinghai Lu72ee9b02005-12-14 02:39:33 +000075
Aaron Durbina146d582013-02-08 16:56:51 -060076 /* Fill in secondary_start's local gdt. */
77 setup_secondary_gdt();
78
Zheng Baod4c5c442010-02-20 09:38:16 +000079 code_size = (unsigned long)_secondary_start_end - (unsigned long)_secondary_start;
Yinghai Lu72ee9b02005-12-14 02:39:33 +000080
Patrick Georgie1667822012-05-05 15:29:32 +020081#if CONFIG_HAVE_ACPI_RESUME
Rudolf Mareka572f832009-04-13 17:57:44 +000082 /* need to save it for RAM resume */
83 lowmem_backup_size = code_size;
84 lowmem_backup = malloc(code_size);
Kyösti Mälkki63539bb2012-07-05 06:31:15 +030085 lowmem_backup_ptr = (char *)AP_SIPI_VECTOR;
Zheng Baod4c5c442010-02-20 09:38:16 +000086
Rudolf Mareka572f832009-04-13 17:57:44 +000087 if (lowmem_backup == NULL)
88 die("Out of backup memory\n");
89
Zheng Baod4c5c442010-02-20 09:38:16 +000090 memcpy(lowmem_backup, lowmem_backup_ptr, lowmem_backup_size);
Rudolf Mareka572f832009-04-13 17:57:44 +000091#endif
Zheng Baod4c5c442010-02-20 09:38:16 +000092 /* copy the _secondary_start to the ram below 1M*/
Kyösti Mälkki63539bb2012-07-05 06:31:15 +030093 memcpy((unsigned char *)AP_SIPI_VECTOR, (unsigned char *)_secondary_start, code_size);
Yinghai Lu72ee9b02005-12-14 02:39:33 +000094
Stefan Reinauer1bfbbc02012-06-07 14:00:07 -070095 printk(BIOS_DEBUG, "start_eip=0x%08lx, code_size=0x%08lx\n",
96 (long unsigned int)AP_SIPI_VECTOR, code_size);
Yinghai Lu72ee9b02005-12-14 02:39:33 +000097}
98
Sven Schnelle51676b12012-07-29 19:18:03 +020099static int lapic_start_cpu(unsigned long apicid)
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000100{
101 int timeout;
Kyösti Mälkki63539bb2012-07-05 06:31:15 +0300102 unsigned long send_status, accept_status;
Sven Schnelle51676b12012-07-29 19:18:03 +0200103 int j, num_starts, maxlvt;
Zheng Baod4c5c442010-02-20 09:38:16 +0000104
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000105 /*
106 * Starting actual IPI sequence...
107 */
108
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000109 printk(BIOS_SPEW, "Asserting INIT.\n");
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000110
Sven Schnelle51676b12012-07-29 19:18:03 +0200111 /*
112 * Turn INIT on target chip
113 */
114 lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000115
Sven Schnelle51676b12012-07-29 19:18:03 +0200116 /*
117 * Send IPI
118 */
119
120 lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT
121 | LAPIC_DM_INIT);
122
123 printk(BIOS_SPEW, "Waiting for send to finish...\n");
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000124 timeout = 0;
125 do {
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000126 printk(BIOS_SPEW, "+");
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000127 udelay(100);
128 send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
129 } while (send_status && (timeout++ < 1000));
130 if (timeout >= 1000) {
Stefan Reinauer1bfbbc02012-06-07 14:00:07 -0700131 printk(BIOS_ERR, "CPU %ld: First APIC write timed out. "
132 "Disabling\n", apicid);
Zheng Baod4c5c442010-02-20 09:38:16 +0000133 // too bad.
Sven Schnelle51676b12012-07-29 19:18:03 +0200134 printk(BIOS_ERR, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR));
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000135 if (lapic_read(LAPIC_ESR)) {
Sven Schnelle51676b12012-07-29 19:18:03 +0200136 printk(BIOS_ERR, "Try to reset ESR\n");
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000137 lapic_write_around(LAPIC_ESR, 0);
Stefan Reinauer1bfbbc02012-06-07 14:00:07 -0700138 printk(BIOS_ERR, "ESR is 0x%lx\n",
139 lapic_read(LAPIC_ESR));
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000140 }
141 return 0;
142 }
Sven Schnelle51676b12012-07-29 19:18:03 +0200143#if !CONFIG_CPU_AMD_MODEL_10XXX && !CONFIG_CPU_INTEL_MODEL_206AX
144 mdelay(10);
145#endif
Yinghai Lu9a791df2006-04-03 20:38:34 +0000146
Sven Schnelle51676b12012-07-29 19:18:03 +0200147 printk(BIOS_SPEW, "Deasserting INIT.\n");
Sven Schnelle042c1462012-06-17 10:32:55 +0200148
149 /* Target chip */
Sven Schnelle51676b12012-07-29 19:18:03 +0200150 lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
Sven Schnelle042c1462012-06-17 10:32:55 +0200151
Sven Schnelle51676b12012-07-29 19:18:03 +0200152 /* Send IPI */
153 lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT);
Sven Schnelle042c1462012-06-17 10:32:55 +0200154
Sven Schnelle51676b12012-07-29 19:18:03 +0200155 printk(BIOS_SPEW, "Waiting for send to finish...\n");
Sven Schnelle042c1462012-06-17 10:32:55 +0200156 timeout = 0;
157 do {
Sven Schnelle51676b12012-07-29 19:18:03 +0200158 printk(BIOS_SPEW, "+");
Sven Schnelle042c1462012-06-17 10:32:55 +0200159 udelay(100);
160 send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
161 } while (send_status && (timeout++ < 1000));
Sven Schnelle51676b12012-07-29 19:18:03 +0200162 if (timeout >= 1000) {
Stefan Reinauer1bfbbc02012-06-07 14:00:07 -0700163 printk(BIOS_ERR, "CPU %ld: Second apic write timed out. "
164 "Disabling\n", apicid);
Sven Schnelle51676b12012-07-29 19:18:03 +0200165 // too bad.
166 return 0;
167 }
168
169#if !CONFIG_CPU_AMD_MODEL_10XXX
170 num_starts = 2;
171#else
172 num_starts = 1;
173#endif
Sven Schnelle042c1462012-06-17 10:32:55 +0200174
175 /*
Sven Schnelle51676b12012-07-29 19:18:03 +0200176 * Run STARTUP IPI loop.
Sven Schnelle042c1462012-06-17 10:32:55 +0200177 */
Sven Schnelle51676b12012-07-29 19:18:03 +0200178 printk(BIOS_SPEW, "#startup loops: %d.\n", num_starts);
179
180 maxlvt = 4;
181
182 for (j = 1; j <= num_starts; j++) {
183 printk(BIOS_SPEW, "Sending STARTUP #%d to %lu.\n", j, apicid);
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000184 lapic_read_around(LAPIC_SPIV);
185 lapic_write(LAPIC_ESR, 0);
Sven Schnelle51676b12012-07-29 19:18:03 +0200186 lapic_read(LAPIC_ESR);
187 printk(BIOS_SPEW, "After apic_write.\n");
Sven Schnelle042c1462012-06-17 10:32:55 +0200188
Sven Schnelle51676b12012-07-29 19:18:03 +0200189 /*
190 * STARTUP IPI
191 */
192
193 /* Target chip */
194 lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
195
196 /* Boot on the stack */
197 /* Kick the second */
198 lapic_write_around(LAPIC_ICR, LAPIC_DM_STARTUP
199 | (AP_SIPI_VECTOR >> 12));
200
201 /*
202 * Give the other CPU some time to accept the IPI.
203 */
204 udelay(300);
205
206 printk(BIOS_SPEW, "Startup point 1.\n");
207
208 printk(BIOS_SPEW, "Waiting for send to finish...\n");
209 timeout = 0;
210 do {
211 printk(BIOS_SPEW, "+");
212 udelay(100);
213 send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
214 } while (send_status && (timeout++ < 1000));
215
216 /*
217 * Give the other CPU some time to accept the IPI.
218 */
219 udelay(200);
220 /*
221 * Due to the Pentium erratum 3AP.
222 */
223 if (maxlvt > 3) {
224 lapic_read_around(LAPIC_SPIV);
225 lapic_write(LAPIC_ESR, 0);
226 }
227 accept_status = (lapic_read(LAPIC_ESR) & 0xEF);
228 if (send_status || accept_status)
229 break;
230 }
231 printk(BIOS_SPEW, "After Startup.\n");
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000232 if (send_status)
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000233 printk(BIOS_WARNING, "APIC never delivered???\n");
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000234 if (accept_status)
Stefan Reinauer1bfbbc02012-06-07 14:00:07 -0700235 printk(BIOS_WARNING, "APIC delivery error (%lx).\n",
236 accept_status);
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000237 if (send_status || accept_status)
238 return 0;
239 return 1;
240}
241
Stefan Reinauerf8ee1802008-01-18 15:08:58 +0000242/* Number of cpus that are currently running in coreboot */
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000243static atomic_t active_cpus = ATOMIC_INIT(1);
244
Sven Schnelle51676b12012-07-29 19:18:03 +0200245/* start_cpu_lock covers last_cpu_index and secondary_stack.
246 * Only starting one cpu at a time let's me remove the logic
247 * for select the stack from assembly language.
248 *
249 * In addition communicating by variables to the cpu I
Ronald G. Minnich8b930592012-06-05 14:41:27 -0700250 * am starting allows me to verify it has started before
Sven Schnelle51676b12012-07-29 19:18:03 +0200251 * start_cpu returns.
252 */
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000253
Sven Schnelle51676b12012-07-29 19:18:03 +0200254static spinlock_t start_cpu_lock = SPIN_LOCK_UNLOCKED;
Ronald G. Minnich8b930592012-06-05 14:41:27 -0700255static unsigned int last_cpu_index = 0;
Stefan Reinauer1bfbbc02012-06-07 14:00:07 -0700256static void *stacks[CONFIG_MAX_CPUS];
Sven Schnelle51676b12012-07-29 19:18:03 +0200257volatile unsigned long secondary_stack;
Ronald G. Minnich8b930592012-06-05 14:41:27 -0700258volatile unsigned int secondary_cpu_index;
Sven Schnelle51676b12012-07-29 19:18:03 +0200259
260int start_cpu(device_t cpu)
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000261{
Sven Schnelle51676b12012-07-29 19:18:03 +0200262 struct cpu_info *info;
263 unsigned long stack_end;
Ronald G. Minnich000bf832012-06-06 13:00:24 -0700264 unsigned long stack_base;
265 unsigned long *stack;
Sven Schnelle51676b12012-07-29 19:18:03 +0200266 unsigned long apicid;
Ronald G. Minnich8b930592012-06-05 14:41:27 -0700267 unsigned int index;
Sven Schnelle51676b12012-07-29 19:18:03 +0200268 unsigned long count;
Ronald G. Minnich000bf832012-06-06 13:00:24 -0700269 int i;
Sven Schnelle51676b12012-07-29 19:18:03 +0200270 int result;
271
272 spin_lock(&start_cpu_lock);
273
Stefan Reinauer1bfbbc02012-06-07 14:00:07 -0700274 /* Get the CPU's apicid */
Sven Schnelle51676b12012-07-29 19:18:03 +0200275 apicid = cpu->path.apic.apic_id;
276
277 /* Get an index for the new processor */
278 index = ++last_cpu_index;
279
Stefan Reinauer1bfbbc02012-06-07 14:00:07 -0700280 /* Find end of the new processor's stack */
281 stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) -
282 sizeof(struct cpu_info);
Sven Schnelle51676b12012-07-29 19:18:03 +0200283
Ronald G. Minnich000bf832012-06-06 13:00:24 -0700284 stack_base = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*(index+1));
Ronald G. Minnich8b930592012-06-05 14:41:27 -0700285 printk(BIOS_SPEW, "CPU%d: stack_base %p, stack_end %p\n", index,
Ronald G. Minnich000bf832012-06-06 13:00:24 -0700286 (void *)stack_base, (void *)stack_end);
287 /* poison the stack */
288 for(stack = (void *)stack_base, i = 0; i < CONFIG_STACK_SIZE; i++)
289 stack[i/sizeof(*stack)] = 0xDEADBEEF;
290 stacks[index] = stack;
Stefan Reinauer1bfbbc02012-06-07 14:00:07 -0700291 /* Record the index and which CPU structure we are using */
Sven Schnelle51676b12012-07-29 19:18:03 +0200292 info = (struct cpu_info *)stack_end;
293 info->index = index;
294 info->cpu = cpu;
295
Ronald G. Minnich8b930592012-06-05 14:41:27 -0700296 /* Advertise the new stack and index to start_cpu */
Sven Schnelle51676b12012-07-29 19:18:03 +0200297 secondary_stack = stack_end;
Ronald G. Minnich8b930592012-06-05 14:41:27 -0700298 secondary_cpu_index = index;
Sven Schnelle51676b12012-07-29 19:18:03 +0200299
Stefan Reinauer1bfbbc02012-06-07 14:00:07 -0700300 /* Until the CPU starts up report the CPU is not enabled */
Sven Schnelle51676b12012-07-29 19:18:03 +0200301 cpu->enabled = 0;
302 cpu->initialized = 0;
303
304 /* Start the cpu */
305 result = lapic_start_cpu(apicid);
306
307 if (result) {
308 result = 0;
309 /* Wait 1s or until the new cpu calls in */
310 for(count = 0; count < 100000 ; count++) {
311 if (secondary_stack == 0) {
312 result = 1;
313 break;
314 }
315 udelay(10);
316 }
317 }
318 secondary_stack = 0;
319 spin_unlock(&start_cpu_lock);
320 return result;
321}
322
323#if CONFIG_AP_IN_SIPI_WAIT
324
325/**
Stefan Reinauer1bfbbc02012-06-07 14:00:07 -0700326 * Sending INIT IPI to self is equivalent of asserting #INIT with a bit of
327 * delay.
Sven Schnelle51676b12012-07-29 19:18:03 +0200328 * An undefined number of instruction cycles will complete. All global locks
329 * must be released before INIT IPI and no printk is allowed after this.
330 * De-asserting INIT IPI is a no-op on later Intel CPUs.
331 *
332 * If you set DEBUG_HALT_SELF to 1, printk's after INIT IPI are enabled
333 * but running thread may halt without releasing the lock and effectively
334 * deadlock other CPUs.
335 */
336#define DEBUG_HALT_SELF 0
337
338/**
339 * Normally this function is defined in lapic.h as an always inline function
340 * that just keeps the CPU in a hlt() loop. This does not work on all CPUs.
341 * I think all hyperthreading CPUs might need this version, but I could only
342 * verify this on the Intel Core Duo
343 */
344void stop_this_cpu(void)
345{
Sven Schnelle042c1462012-06-17 10:32:55 +0200346 int timeout;
Sven Schnelle51676b12012-07-29 19:18:03 +0200347 unsigned long send_status;
348 unsigned long id;
349
350 id = lapic_read(LAPIC_ID) >> 24;
351
352 printk(BIOS_DEBUG, "CPU %ld going down...\n", id);
353
354 /* send an LAPIC INIT to myself */
355 lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(id));
Stefan Reinauer1bfbbc02012-06-07 14:00:07 -0700356 lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG |
357 LAPIC_INT_ASSERT | LAPIC_DM_INIT);
Stefan Reinauer68524062008-08-02 15:15:23 +0000358
359 /* wait for the ipi send to finish */
Sven Schnelle51676b12012-07-29 19:18:03 +0200360#if DEBUG_HALT_SELF
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000361 printk(BIOS_SPEW, "Waiting for send to finish...\n");
Sven Schnelle51676b12012-07-29 19:18:03 +0200362#endif
Stefan Reinauer68524062008-08-02 15:15:23 +0000363 timeout = 0;
364 do {
Sven Schnelle51676b12012-07-29 19:18:03 +0200365#if DEBUG_HALT_SELF
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000366 printk(BIOS_SPEW, "+");
Sven Schnelle51676b12012-07-29 19:18:03 +0200367#endif
Stefan Reinauer68524062008-08-02 15:15:23 +0000368 udelay(100);
369 send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
370 } while (send_status && (timeout++ < 1000));
371 if (timeout >= 1000) {
Sven Schnelle51676b12012-07-29 19:18:03 +0200372#if DEBUG_HALT_SELF
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000373 printk(BIOS_ERR, "timed out\n");
Sven Schnelle51676b12012-07-29 19:18:03 +0200374#endif
Stefan Reinauer68524062008-08-02 15:15:23 +0000375 }
376 mdelay(10);
Sven Schnelle51676b12012-07-29 19:18:03 +0200377
378#if DEBUG_HALT_SELF
379 printk(BIOS_SPEW, "Deasserting INIT.\n");
380#endif
381 /* Deassert the LAPIC INIT */
382 lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(id));
383 lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT);
384
385#if DEBUG_HALT_SELF
386 printk(BIOS_SPEW, "Waiting for send to finish...\n");
387#endif
388 timeout = 0;
389 do {
390#if DEBUG_HALT_SELF
391 printk(BIOS_SPEW, "+");
392#endif
393 udelay(100);
394 send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
395 } while (send_status && (timeout++ < 1000));
396 if (timeout >= 1000) {
397#if DEBUG_HALT_SELF
398 printk(BIOS_ERR, "timed out\n");
399#endif
400 }
401
402 while(1) {
403 hlt();
404 }
Stefan Reinauer68524062008-08-02 15:15:23 +0000405}
Sven Schnelle51676b12012-07-29 19:18:03 +0200406#endif
Stefan Reinauer68524062008-08-02 15:15:23 +0000407
efdesign983cab93c2011-07-20 20:11:46 -0600408#ifdef __SSE3__
409static __inline__ __attribute__((always_inline)) unsigned long readcr4(void)
410{
411 unsigned long value;
412 __asm__ __volatile__ (
413 "mov %%cr4, %[value]"
414 : [value] "=a" (value));
415 return value;
416}
417
418static __inline__ __attribute__((always_inline)) void writecr4(unsigned long Data)
419{
420 __asm__ __volatile__ (
421 "mov %%eax, %%cr4"
422 :
423 : "a" (Data)
424 );
425}
426#endif
427
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000428/* C entry point of secondary cpus */
Stefan Reinauer399486e2012-12-06 13:54:29 -0800429void asmlinkage secondary_cpu_init(unsigned int index)
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000430{
Sven Schnelle042c1462012-06-17 10:32:55 +0200431 atomic_inc(&active_cpus);
Sven Schnelle51676b12012-07-29 19:18:03 +0200432#if CONFIG_SERIAL_CPU_INIT
433 spin_lock(&start_cpu_lock);
434#endif
435
436#ifdef __SSE3__
437 /*
438 * Seems that CR4 was cleared when AP start via lapic_start_cpu()
439 * Turn on CR4.OSFXSR and CR4.OSXMMEXCPT when SSE options enabled
440 */
441 u32 cr4_val;
442 cr4_val = readcr4();
443 cr4_val |= (1 << 9 | 1 << 10);
444 writecr4(cr4_val);
445#endif
Ronald G. Minnich8b930592012-06-05 14:41:27 -0700446 cpu_initialize(index);
Sven Schnelle51676b12012-07-29 19:18:03 +0200447#if CONFIG_SERIAL_CPU_INIT
448 spin_unlock(&start_cpu_lock);
449#endif
450
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000451 atomic_dec(&active_cpus);
Sven Schnelle51676b12012-07-29 19:18:03 +0200452
453 stop_this_cpu();
454}
455
456static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu)
457{
458 device_t cpu;
459 /* Loop through the cpus once getting them started */
460
461 for(cpu = cpu_bus->children; cpu ; cpu = cpu->sibling) {
462 if (cpu->path.type != DEVICE_PATH_APIC) {
463 continue;
464 }
465 #if !CONFIG_SERIAL_CPU_INIT
466 if(cpu==bsp_cpu) {
467 continue;
468 }
469 #endif
470
471 if (!cpu->enabled) {
472 continue;
473 }
474
475 if (cpu->initialized) {
476 continue;
477 }
478
479 if (!start_cpu(cpu)) {
480 /* Record the error in cpu? */
481 printk(BIOS_ERR, "CPU 0x%02x would not start!\n",
482 cpu->path.apic.apic_id);
483 }
484#if CONFIG_SERIAL_CPU_INIT
485 udelay(10);
486#endif
487 }
488
Yinghai Lu9a8e36d2006-05-18 17:02:17 +0000489}
490
491static void wait_other_cpus_stop(struct bus *cpu_bus)
492{
493 device_t cpu;
494 int old_active_count, active_count;
Stefan Reinauer2bdfb482012-04-03 16:17:11 -0700495 long loopcount = 0;
Ronald G. Minnich000bf832012-06-06 13:00:24 -0700496 int i;
Stefan Reinauer2bdfb482012-04-03 16:17:11 -0700497
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000498 /* Now loop until the other cpus have finished initializing */
499 old_active_count = 1;
500 active_count = atomic_read(&active_cpus);
501 while(active_count > 1) {
502 if (active_count != old_active_count) {
Stefan Reinauer1bfbbc02012-06-07 14:00:07 -0700503 printk(BIOS_INFO, "Waiting for %d CPUS to stop\n",
504 active_count - 1);
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000505 old_active_count = active_count;
506 }
507 udelay(10);
508 active_count = atomic_read(&active_cpus);
Stefan Reinauer2bdfb482012-04-03 16:17:11 -0700509 loopcount++;
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000510 }
Eric Biederman7003ba42004-10-16 06:20:29 +0000511 for(cpu = cpu_bus->children; cpu; cpu = cpu->sibling) {
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000512 if (cpu->path.type != DEVICE_PATH_APIC) {
513 continue;
514 }
Stefan Reinauer2bdfb482012-04-03 16:17:11 -0700515 if (cpu->path.apic.apic_id == SPEEDSTEP_APIC_MAGIC) {
516 continue;
517 }
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000518 if (!cpu->initialized) {
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000519 printk(BIOS_ERR, "CPU 0x%02x did not initialize!\n",
Stefan Reinauer2b34db82009-02-28 20:10:20 +0000520 cpu->path.apic.apic_id);
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000521 }
522 }
Stefan Reinauer2bdfb482012-04-03 16:17:11 -0700523 printk(BIOS_DEBUG, "All AP CPUs stopped (%ld loops)\n", loopcount);
Stefan Reinauer75dbc382012-10-15 15:19:43 -0700524 for(i = 1; i <= last_cpu_index; i++)
525 checkstack((void *)stacks[i] + CONFIG_STACK_SIZE, i);
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000526}
527
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000528#endif /* CONFIG_SMP */
529
Eric Biederman7003ba42004-10-16 06:20:29 +0000530void initialize_cpus(struct bus *cpu_bus)
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000531{
532 struct device_path cpu_path;
Sven Schnelle51676b12012-07-29 19:18:03 +0200533 struct cpu_info *info;
534
535 /* Find the info struct for this cpu */
536 info = cpu_info();
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000537
538#if NEED_LAPIC == 1
539 /* Ensure the local apic is enabled */
540 enable_lapic();
541
542 /* Get the device path of the boot cpu */
543 cpu_path.type = DEVICE_PATH_APIC;
Stefan Reinauer2b34db82009-02-28 20:10:20 +0000544 cpu_path.apic.apic_id = lapicid();
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000545#else
546 /* Get the device path of the boot cpu */
Eric Biedermana9e632c2004-11-18 22:38:08 +0000547 cpu_path.type = DEVICE_PATH_CPU;
Stefan Reinauer2b34db82009-02-28 20:10:20 +0000548 cpu_path.cpu.id = 0;
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000549#endif
Stefan Reinauer00a889c2008-10-29 04:48:44 +0000550
Sven Schnelle51676b12012-07-29 19:18:03 +0200551 /* Find the device structure for the boot cpu */
552 info->cpu = alloc_find_dev(cpu_bus, &cpu_path);
553
Ronald G. Minnich000bf832012-06-06 13:00:24 -0700554#if CONFIG_SMP && CONFIG_MAX_CPUS > 1
Stefan Reinauer1bfbbc02012-06-07 14:00:07 -0700555 // why here? In case some day we can start core1 in amd_sibling_init
556 copy_secondary_start_to_lowest_1M();
Yinghai Lu3a68aeb2006-01-09 20:42:50 +0000557#endif
Stefan Reinauer00a889c2008-10-29 04:48:44 +0000558
Stefan Reinauer08670622009-06-30 15:17:49 +0000559#if CONFIG_HAVE_SMI_HANDLER
Stefan Reinauer00a889c2008-10-29 04:48:44 +0000560 smm_init();
561#endif
562
Ronald G. Minnich000bf832012-06-06 13:00:24 -0700563#if CONFIG_SMP && CONFIG_MAX_CPUS > 1
Sven Schnelle51676b12012-07-29 19:18:03 +0200564 #if !CONFIG_SERIAL_CPU_INIT
565 /* start all aps at first, so we can init ECC all together */
566 start_other_cpus(cpu_bus, info->cpu);
567 #endif
568#endif
569
Zheng Baod4c5c442010-02-20 09:38:16 +0000570 /* Initialize the bootstrap processor */
Ronald G. Minnich8b930592012-06-05 14:41:27 -0700571 cpu_initialize(0);
Yinghai Lu9a8e36d2006-05-18 17:02:17 +0000572
Ronald G. Minnich000bf832012-06-06 13:00:24 -0700573#if CONFIG_SMP && CONFIG_MAX_CPUS > 1
Sven Schnelle51676b12012-07-29 19:18:03 +0200574 #if CONFIG_SERIAL_CPU_INIT
575 start_other_cpus(cpu_bus, info->cpu);
576 #endif
577
Yinghai Lu9a8e36d2006-05-18 17:02:17 +0000578 /* Now wait the rest of the cpus stop*/
579 wait_other_cpus_stop(cpu_bus);
580#endif
Eric Biedermanfcd5ace2004-10-14 19:29:29 +0000581}