| Aaron Durbin | dc9f5cd | 2015-09-08 13:34:43 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| Aaron Durbin | dc9f5cd | 2015-09-08 13:34:43 -0500 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #ifndef __TIMESTAMP_SERIALIZED_H__ |
| 17 | #define __TIMESTAMP_SERIALIZED_H__ |
| 18 | |
| 19 | #include <stdint.h> |
| 20 | |
| 21 | struct timestamp_entry { |
| 22 | uint32_t entry_id; |
| 23 | uint64_t entry_stamp; |
| 24 | } __attribute__((packed)); |
| 25 | |
| 26 | struct timestamp_table { |
| 27 | uint64_t base_time; |
| 28 | uint16_t max_entries; |
| 29 | uint16_t tick_freq_mhz; |
| 30 | uint32_t num_entries; |
| 31 | struct timestamp_entry entries[0]; /* Variable number of entries */ |
| 32 | } __attribute__((packed)); |
| 33 | |
| 34 | enum timestamp_id { |
| 35 | TS_START_ROMSTAGE = 1, |
| 36 | TS_BEFORE_INITRAM = 2, |
| 37 | TS_AFTER_INITRAM = 3, |
| 38 | TS_END_ROMSTAGE = 4, |
| 39 | TS_START_VBOOT = 5, |
| 40 | TS_END_VBOOT = 6, |
| 41 | TS_START_COPYRAM = 8, |
| 42 | TS_END_COPYRAM = 9, |
| 43 | TS_START_RAMSTAGE = 10, |
| 44 | TS_START_BOOTBLOCK = 11, |
| 45 | TS_END_BOOTBLOCK = 12, |
| 46 | TS_START_COPYROM = 13, |
| 47 | TS_END_COPYROM = 14, |
| 48 | TS_START_ULZMA = 15, |
| 49 | TS_END_ULZMA = 16, |
| 50 | TS_DEVICE_ENUMERATE = 30, |
| 51 | TS_DEVICE_CONFIGURE = 40, |
| 52 | TS_DEVICE_ENABLE = 50, |
| 53 | TS_DEVICE_INITIALIZE = 60, |
| 54 | TS_DEVICE_DONE = 70, |
| 55 | TS_CBMEM_POST = 75, |
| 56 | TS_WRITE_TABLES = 80, |
| 57 | TS_LOAD_PAYLOAD = 90, |
| 58 | TS_ACPI_WAKE_JUMP = 98, |
| 59 | TS_SELFBOOT_JUMP = 99, |
| 60 | |
| 61 | /* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */ |
| 62 | TS_START_COPYVER = 501, |
| 63 | TS_END_COPYVER = 502, |
| 64 | TS_START_TPMINIT = 503, |
| 65 | TS_END_TPMINIT = 504, |
| 66 | TS_START_VERIFY_SLOT = 505, |
| 67 | TS_END_VERIFY_SLOT = 506, |
| 68 | TS_START_HASH_BODY = 507, |
| 69 | TS_DONE_LOADING = 508, |
| 70 | TS_DONE_HASHING = 509, |
| 71 | TS_END_HASH_BODY = 510, |
| 72 | |
| 73 | /* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */ |
| 74 | TS_FSP_MEMORY_INIT_START = 950, |
| 75 | TS_FSP_MEMORY_INIT_END = 951, |
| 76 | TS_FSP_TEMP_RAM_EXIT_START = 952, |
| 77 | TS_FSP_TEMP_RAM_EXIT_END = 953, |
| 78 | TS_FSP_SILICON_INIT_START = 954, |
| 79 | TS_FSP_SILICON_INIT_END = 955, |
| 80 | TS_FSP_BEFORE_ENUMERATE = 956, |
| 81 | TS_FSP_AFTER_ENUMERATE = 957, |
| 82 | TS_FSP_BEFORE_FINALIZE = 958, |
| 83 | TS_FSP_AFTER_FINALIZE = 959, |
| 84 | |
| 85 | /* 1000+ reserved for payloads (1000-1200: ChromeOS depthcharge) */ |
| 86 | }; |
| 87 | |
| 88 | #endif |