blob: 02564cf5ba3d522b08d8d9b0f3c10ac477ff4818 [file] [log] [blame]
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001/*
2 * This file is part of the coreboot project.
3 *
Marshall Dawsone7d892c2016-10-08 14:49:41 -06004 * Copyright (C) 2015 - 2016 Advanced Micro Devices, Inc.
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08005 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16/*
17 * ROMSIG At ROMBASE + 0x20000:
zbaoc3b0b722016-02-19 13:47:31 +080018 * 0 4 8 C
Zheng Bao9c7ff7b2015-11-17 22:57:39 +080019 * +------------+---------------+----------------+------------+
20 * | 0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM |
21 * +------------+---------------+----------------+------------+
zbaoc3b0b722016-02-19 13:47:31 +080022 * | PSPDIR ADDR|PSPDIR ADDR |<-- Field 0x14 could be either
23 * +------------+---------------+ 2nd PSP directory or PSP COMBO directory
Zheng Bao9c7ff7b2015-11-17 22:57:39 +080024 * EC ROM should be 64K aligned.
25 *
Zheng Bao4fcc9f22015-11-20 12:29:04 +080026 * PSP directory (Where "PSPDIR ADDR" points)
Zheng Bao9c7ff7b2015-11-17 22:57:39 +080027 * +------------+---------------+----------------+------------+
28 * | 'PSP$' | Fletcher | Count | Reserved |
29 * +------------+---------------+----------------+------------+
30 * | 0 | size | Base address | Reserved | Pubkey
31 * +------------+---------------+----------------+------------+
32 * | 1 | size | Base address | Reserved | Bootloader
33 * +------------+---------------+----------------+------------+
34 * | 8 | size | Base address | Reserved | Smu Firmware
35 * +------------+---------------+----------------+------------+
36 * | 3 | size | Base address | Reserved | Recovery Firmware
37 * +------------+---------------+----------------+------------+
38 * | |
39 * | |
40 * | Other PSP Firmware |
41 * | |
42 * | |
43 * +------------+---------------+----------------+------------+
Zheng Bao4fcc9f22015-11-20 12:29:04 +080044 *
zbaoc3b0b722016-02-19 13:47:31 +080045 * PSP Combo directory
Zheng Bao4fcc9f22015-11-20 12:29:04 +080046 * +------------+---------------+----------------+------------+
zbao6e2f3d12016-02-19 13:34:59 +080047 * | 'PSP2' | Fletcher | Count |Look up mode|
Zheng Bao4fcc9f22015-11-20 12:29:04 +080048 * +------------+---------------+----------------+------------+
zbaoc3a08a92016-03-02 14:47:27 +080049 * | R e s e r v e d |
50 * +------------+---------------+----------------+------------+
zbao6e2f3d12016-02-19 13:34:59 +080051 * | ID-Sel | PSP ID | PSPDIR ADDR | | 2nd PSP directory
Zheng Bao4fcc9f22015-11-20 12:29:04 +080052 * +------------+---------------+----------------+------------+
zbao6e2f3d12016-02-19 13:34:59 +080053 * | ID-Sel | PSP ID | PSPDIR ADDR | | 3rd PSP directory
Zheng Bao4fcc9f22015-11-20 12:29:04 +080054 * +------------+---------------+----------------+------------+
55 * | |
56 * | Other PSP |
57 * | |
58 * +------------+---------------+----------------+------------+
59 *
Zheng Bao9c7ff7b2015-11-17 22:57:39 +080060 */
61
Zheng Bao9c7ff7b2015-11-17 22:57:39 +080062#include <fcntl.h>
63#include <errno.h>
64#include <stdio.h>
65#include <sys/stat.h>
66#include <sys/types.h>
67#include <unistd.h>
68#include <string.h>
69#include <stdlib.h>
70#include <getopt.h>
71
72#ifndef CONFIG_ROM_SIZE
73#define CONFIG_ROM_SIZE 0x400000
74#endif
75
Martin Roth60f15512016-11-08 09:55:01 -070076#define AMD_ROMSIG_OFFSET 0x20000
77#define MIN_ROM_KB 256
Zheng Bao9c7ff7b2015-11-17 22:57:39 +080078
Martin Rothcd15bc82016-11-08 11:34:02 -070079#define ALIGN(val, by) (((val) + (by) - 1) & ~((by) - 1))
Marshall Dawson7c1e1422019-04-11 09:44:43 -060080#define _MAX(A, B) (((A) > (B)) ? (A) : (B))
81#define ERASE_ALIGNMENT 0x1000U
Marshall Dawson2794a862019-03-04 16:53:15 -070082#define TABLE_ALIGNMENT 0x1000U
83#define BLOB_ALIGNMENT 0x100U
Marshall Dawson24f73d42019-04-01 10:48:43 -060084#define TABLE_ERASE_ALIGNMENT _MAX(TABLE_ALIGNMENT, ERASE_ALIGNMENT)
Marshall Dawson7c1e1422019-04-11 09:44:43 -060085#define BLOB_ERASE_ALIGNMENT _MAX(BLOB_ALIGNMENT, ERASE_ALIGNMENT)
Zheng Bao9c7ff7b2015-11-17 22:57:39 +080086
Marshall Dawsonef79fcc2019-04-01 10:16:41 -060087#define DEFAULT_SOFT_FUSE_CHAIN "0x1"
88
Marshall Dawson239286c2019-02-23 16:42:46 -070089#define EMBEDDED_FW_SIGNATURE 0x55aa55aa
Marshall Dawson24f73d42019-04-01 10:48:43 -060090#define PSP_COOKIE 0x50535024 /* 'PSP$' */
91#define PSPL2_COOKIE 0x324c5024 /* '2LP$' */
92#define PSP2_COOKIE 0x50535032 /* 'PSP2' */
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -060093#define BDT1_COOKIE 0x44484224 /* 'DHB$ */
94#define BDT2_COOKIE 0x324c4224 /* '2LB$ */
Marshall Dawson239286c2019-02-23 16:42:46 -070095
Zheng Bao9c7ff7b2015-11-17 22:57:39 +080096/*
Marshall Dawson0e02ce82019-03-04 16:50:37 -070097 * Beginning with Family 15h Models 70h-7F, a.k.a Stoney Ridge, the PSP
98 * can support an optional "combo" implementation. If the PSP sees the
99 * PSP2 cookie, it interprets the table as a roadmap to additional PSP
100 * tables. Using this, support for multiple product generations may be
101 * built into one image. If the PSP$ cookie is found, the table is a
102 * normal directory table.
103 *
104 * Modern generations supporting the combo directories require the
105 * pointer to be at offset 0x14 of the Embedded Firmware Structure,
106 * regardless of the type of directory used. The --combo-capable
107 * argument enforces this placement.
108 *
109 * TODO: Future work may require fully implementing the PSP_COMBO feature.
zbaoc3b0b722016-02-19 13:47:31 +0800110 */
Marshall Dawson0e02ce82019-03-04 16:50:37 -0700111#define PSP_COMBO 0
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800112
Marshall Dawson239286c2019-02-23 16:42:46 -0700113typedef unsigned long long int uint64_t;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800114typedef unsigned int uint32_t;
115typedef unsigned char uint8_t;
116typedef unsigned short uint16_t;
117
118/*
119 * Creates the OSI Fletcher checksum. See 8473-1, Appendix C, section C.3.
120 * The checksum field of the passed PDU does not need to be reset to zero.
121 *
122 * The "Fletcher Checksum" was proposed in a paper by John G. Fletcher of
123 * Lawrence Livermore Labs. The Fletcher Checksum was proposed as an
124 * alternative to cyclical redundancy checks because it provides error-
125 * detection properties similar to cyclical redundancy checks but at the
126 * cost of a simple summation technique. Its characteristics were first
127 * published in IEEE Transactions on Communications in January 1982. One
128 * version has been adopted by ISO for use in the class-4 transport layer
129 * of the network protocol.
130 *
131 * This program expects:
132 * stdin: The input file to compute a checksum for. The input file
133 * not be longer than 256 bytes.
134 * stdout: Copied from the input file with the Fletcher's Checksum
135 * inserted 8 bytes after the beginning of the file.
136 * stderr: Used to print out error messages.
137 */
Marshall Dawson8a45a4d2019-02-24 07:18:44 -0700138static uint32_t fletcher32(const void *data, int length)
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800139{
140 uint32_t c0;
141 uint32_t c1;
142 uint32_t checksum;
143 int index;
Marshall Dawson8a45a4d2019-02-24 07:18:44 -0700144 const uint16_t *pptr = data;
145
146 length /= 2;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800147
148 c0 = 0xFFFF;
149 c1 = 0xFFFF;
150
Marshall Dawsonb85ddc52019-07-23 07:24:30 -0600151 while (length) {
152 index = length >= 359 ? 359 : length;
153 length -= index;
154 do {
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800155 c0 += *(pptr++);
156 c1 += c0;
Marshall Dawsonb85ddc52019-07-23 07:24:30 -0600157 } while (--index);
158 c0 = (c0 & 0xFFFF) + (c0 >> 16);
159 c1 = (c1 & 0xFFFF) + (c1 >> 16);
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800160 }
161
Marshall Dawson8a45a4d2019-02-24 07:18:44 -0700162 /* Sums[0,1] mod 64K + overflow */
163 c0 = (c0 & 0xFFFF) + (c0 >> 16);
164 c1 = (c1 & 0xFFFF) + (c1 >> 16);
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800165 checksum = (c1 << 16) | c0;
166
167 return checksum;
168}
169
Martin Roth8806f7f2016-11-08 10:44:18 -0700170static void usage(void)
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800171{
Martin Roth0e940622016-11-08 10:37:53 -0700172 printf("amdfwtool: Create AMD Firmware combination\n");
173 printf("Usage: amdfwtool [options] -f <size> -o <filename>\n");
Marshall Dawsonf4b9b412017-03-17 16:30:51 -0600174 printf("-x | --xhci <FILE> Add XHCI blob\n");
175 printf("-i | --imc <FILE> Add IMC blob\n");
176 printf("-g | --gec <FILE> Add GEC blob\n");
Martin Roth0e940622016-11-08 10:37:53 -0700177
178 printf("\nPSP options:\n");
Marshall Dawson67d868d2019-02-28 11:43:40 -0700179 printf("-A | --combo-capable Place PSP directory pointer at Embedded Firmware\n");
180 printf(" offset able to support combo directory\n");
Marshall Dawson24f73d42019-04-01 10:48:43 -0600181 printf("-M | --multilevel Generate primary and secondary tables\n");
Marshall Dawsonf4b9b412017-03-17 16:30:51 -0600182 printf("-p | --pubkey <FILE> Add pubkey\n");
183 printf("-b | --bootloader <FILE> Add bootloader\n");
Marshall Dawsondbae6322019-03-04 10:31:03 -0700184 printf("-S | --subprogram <number> Sets subprogram field for the next firmware\n");
Marshall Dawsonf4b9b412017-03-17 16:30:51 -0600185 printf("-s | --smufirmware <FILE> Add smufirmware\n");
186 printf("-r | --recovery <FILE> Add recovery\n");
187 printf("-k | --rtmpubkey <FILE> Add rtmpubkey\n");
188 printf("-c | --secureos <FILE> Add secureos\n");
189 printf("-n | --nvram <FILE> Add nvram\n");
190 printf("-d | --securedebug <FILE> Add securedebug\n");
191 printf("-t | --trustlets <FILE> Add trustlets\n");
192 printf("-u | --trustletkey <FILE> Add trustletkey\n");
193 printf("-w | --smufirmware2 <FILE> Add smufirmware2\n");
194 printf("-m | --smuscs <FILE> Add smuscs\n");
Marshall Dawsonef79fcc2019-04-01 10:16:41 -0600195 printf("-T | --soft-fuse <HEX_VAL> Override default soft fuse values\n");
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600196 printf("-z | --abl-image <FILE> Add AGESA Binary\n");
197 printf("-J | --sec-gasket <FILE> Add security gasket\n");
198 printf("-B | --mp2-fw <FILE> Add MP2 firmware\n");
199 printf("-N | --secdebug <FILE> Add secure unlock image\n");
200 printf("-U | --token-unlock Reserve space for debug token\n");
201 printf("-K | --drv-entry-pts <FILE> Add PSP driver entry points\n");
202 printf("-L | --ikek <FILE> Add Wrapped iKEK\n");
203 printf("-Y | --s0i3drv <FILE> Add s0i3 driver\n");
Martin Rothd3ce8c82019-07-13 20:13:07 -0600204 printf("-Z | --verstage <FILE> Add verstage\n");
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600205 printf("\nBIOS options:\n");
206 printf("-I | --instance <number> Sets instance field for the next BIOS firmware\n");
207 printf("-a | --apcb <FILE> Add AGESA PSP customization block\n");
208 printf("-Q | --apob-base <HEX_VAL> Destination for AGESA PSP output block\n");
209 printf("-F | --apob-nv-base <HEX_VAL> Location of S3 resume data\n");
210 printf("-H | --apob-nv-size <HEX_VAL> Size of S3 resume data\n");
211 printf("-y | --pmu-inst <FILE> Add PMU firmware instruction portion\n");
212 printf("-G | --pmu-data <FILE> Add PMU firmware data portion\n");
Martin Rothec933132019-07-13 20:03:34 -0600213 printf("-O | --ucode <FILE> Add microcode patch\n");
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600214 printf("-X | --mp2-config <FILE> Add MP2 configuration\n");
215 printf("-V | --bios-bin <FILE> Add compressed image; auto source address\n");
216 printf("-e | --bios-bin-src <HEX_VAL> Address in flash of source if -V not used\n");
217 printf("-v | --bios-bin-dest <HEX_VAL> Destination for uncompressed BIOS\n");
218 printf("-j | --bios-uncomp-size <HEX> Uncompressed size of BIOS image\n");
Martin Roth0e940622016-11-08 10:37:53 -0700219 printf("\n-o | --output <filename> output filename\n");
Marshall Dawsonf4b9b412017-03-17 16:30:51 -0600220 printf("-f | --flashsize <HEX_VAL> ROM size in bytes\n");
221 printf(" size must be larger than %dKB\n",
Martin Roth0e940622016-11-08 10:37:53 -0700222 MIN_ROM_KB);
Marshall Dawsonf4b9b412017-03-17 16:30:51 -0600223 printf(" and must a multiple of 1024\n");
Martin Roth0d3b1182017-10-03 14:16:04 -0600224 printf("-l | --location Location of Directory\n");
Marshall Dawsonf4b9b412017-03-17 16:30:51 -0600225 printf("-h | --help show this help\n");
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800226}
227
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600228typedef enum _amd_bios_type {
229 AMD_BIOS_APCB = 0x60,
230 AMD_BIOS_APOB = 0x61,
231 AMD_BIOS_BIN = 0x62,
232 AMD_BIOS_APOB_NV = 0x63,
233 AMD_BIOS_PMUI = 0x64,
234 AMD_BIOS_PMUD = 0x65,
235 AMD_BIOS_UCODE = 0x66,
236 AMD_BIOS_APCB_BK = 0x68,
237 AMD_BIOS_MP2_CFG = 0x6a,
238 AMD_BIOS_L2_PTR = 0x70,
239 AMD_BIOS_INVALID,
240} amd_bios_type;
241
242#define BDT_LVL1 0x1
243#define BDT_LVL2 0x2
244#define BDT_BOTH (BDT_LVL1 | BDT_LVL2)
245typedef struct _amd_bios_entry {
246 amd_bios_type type;
247 int region_type;
248 int reset;
249 int copy;
250 int ro;
251 int zlib;
252 int inst;
253 int subpr;
254 uint64_t src;
255 uint64_t dest;
256 size_t size;
257 char *filename;
258 int level;
259} amd_bios_entry;
260
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800261typedef enum _amd_fw_type {
262 AMD_FW_PSP_PUBKEY = 0,
263 AMD_FW_PSP_BOOTLOADER = 1,
264 AMD_FW_PSP_SMU_FIRMWARE = 8,
265 AMD_FW_PSP_RECOVERY = 3,
266 AMD_FW_PSP_RTM_PUBKEY = 5,
267 AMD_FW_PSP_SECURED_OS = 2,
268 AMD_FW_PSP_NVRAM = 4,
269 AMD_FW_PSP_SECURED_DEBUG = 9,
270 AMD_FW_PSP_TRUSTLETS = 12,
271 AMD_FW_PSP_TRUSTLETKEY = 13,
272 AMD_FW_PSP_SMU_FIRMWARE2 = 18,
273 AMD_PSP_FUSE_CHAIN = 11,
274 AMD_FW_PSP_SMUSCS = 95,
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600275 AMD_DEBUG_UNLOCK = 0x13,
276 AMD_WRAPPED_IKEK = 0x21,
277 AMD_TOKEN_UNLOCK = 0x22,
278 AMD_SEC_GASKET = 0x24,
279 AMD_MP2_FW = 0x25,
280 AMD_DRIVER_ENTRIES = 0x28,
281 AMD_S0I3_DRIVER = 0x2d,
282 AMD_ABL0 = 0x30,
283 AMD_ABL1 = 0x31,
284 AMD_ABL2 = 0x32,
285 AMD_ABL3 = 0x33,
286 AMD_ABL4 = 0x34,
287 AMD_ABL5 = 0x35,
288 AMD_ABL6 = 0x36,
289 AMD_ABL7 = 0x37,
290 AMD_FW_PSP_WHITELIST = 0x3a,
Marshall Dawson24f73d42019-04-01 10:48:43 -0600291 AMD_FW_L2_PTR = 0x40,
Martin Rothd3ce8c82019-07-13 20:13:07 -0600292 AMD_FW_PSP_VERSTAGE = 0x52,
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800293 AMD_FW_IMC,
294 AMD_FW_GEC,
295 AMD_FW_XHCI,
zbaoc3a08a92016-03-02 14:47:27 +0800296 AMD_FW_INVALID,
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800297} amd_fw_type;
298
Marshall Dawson24f73d42019-04-01 10:48:43 -0600299#define PSP_LVL1 0x1
300#define PSP_LVL2 0x2
301#define PSP_BOTH (PSP_LVL1 | PSP_LVL2)
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800302typedef struct _amd_fw_entry {
303 amd_fw_type type;
Marshall Dawsondbae6322019-03-04 10:31:03 -0700304 uint8_t subprog;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800305 char *filename;
Marshall Dawson24f73d42019-04-01 10:48:43 -0600306 int level;
Marshall Dawsonef79fcc2019-04-01 10:16:41 -0600307 uint64_t other;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800308} amd_fw_entry;
309
Martin Roth8806f7f2016-11-08 10:44:18 -0700310static amd_fw_entry amd_psp_fw_table[] = {
Marshall Dawson24f73d42019-04-01 10:48:43 -0600311 { .type = AMD_FW_PSP_PUBKEY, .level = PSP_BOTH },
312 { .type = AMD_FW_PSP_BOOTLOADER, .level = PSP_BOTH },
313 { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 0, .level = PSP_BOTH },
314 { .type = AMD_FW_PSP_RECOVERY, .level = PSP_LVL1 },
315 { .type = AMD_FW_PSP_RTM_PUBKEY, .level = PSP_BOTH },
316 { .type = AMD_FW_PSP_SECURED_OS, .level = PSP_LVL2 },
317 { .type = AMD_FW_PSP_NVRAM, .level = PSP_LVL2 },
318 { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 2, .level = PSP_BOTH },
319 { .type = AMD_FW_PSP_SECURED_DEBUG, .level = PSP_LVL2 },
320 { .type = AMD_FW_PSP_TRUSTLETS, .level = PSP_LVL2 },
321 { .type = AMD_FW_PSP_TRUSTLETKEY, .level = PSP_LVL2 },
322 { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 2, .level = PSP_BOTH },
323 { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH },
324 { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH },
325 { .type = AMD_FW_PSP_SMU_FIRMWARE2, .level = PSP_BOTH },
326 { .type = AMD_FW_PSP_SMUSCS, .level = PSP_BOTH },
327 { .type = AMD_PSP_FUSE_CHAIN, .level = PSP_LVL2 },
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600328 { .type = AMD_DEBUG_UNLOCK, .level = PSP_LVL2 },
329 { .type = AMD_WRAPPED_IKEK, .level = PSP_BOTH },
330 { .type = AMD_TOKEN_UNLOCK, .level = PSP_BOTH },
331 { .type = AMD_SEC_GASKET, .subprog = 2, .level = PSP_BOTH },
332 { .type = AMD_SEC_GASKET, .subprog = 1, .level = PSP_BOTH },
333 { .type = AMD_MP2_FW, .subprog = 2, .level = PSP_LVL2 },
334 { .type = AMD_MP2_FW, .subprog = 1, .level = PSP_LVL2 },
335 { .type = AMD_DRIVER_ENTRIES, .level = PSP_LVL2 },
336 { .type = AMD_S0I3_DRIVER, .level = PSP_LVL2 },
337 { .type = AMD_ABL0, .level = PSP_BOTH },
338 { .type = AMD_ABL1, .level = PSP_BOTH },
339 { .type = AMD_ABL2, .level = PSP_BOTH },
340 { .type = AMD_ABL3, .level = PSP_BOTH },
341 { .type = AMD_ABL4, .level = PSP_BOTH },
342 { .type = AMD_ABL5, .level = PSP_BOTH },
343 { .type = AMD_ABL6, .level = PSP_BOTH },
344 { .type = AMD_ABL7, .level = PSP_BOTH },
Marshall Dawson24f73d42019-04-01 10:48:43 -0600345 { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH },
346 { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH },
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600347 { .type = AMD_FW_PSP_WHITELIST, .level = PSP_LVL2 },
Martin Rothd3ce8c82019-07-13 20:13:07 -0600348 { .type = AMD_FW_PSP_VERSTAGE, .level = PSP_BOTH },
zbaoc3a08a92016-03-02 14:47:27 +0800349 { .type = AMD_FW_INVALID },
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800350};
351
Martin Roth8806f7f2016-11-08 10:44:18 -0700352static amd_fw_entry amd_fw_table[] = {
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800353 { .type = AMD_FW_XHCI },
354 { .type = AMD_FW_IMC },
355 { .type = AMD_FW_GEC },
zbaoc3a08a92016-03-02 14:47:27 +0800356 { .type = AMD_FW_INVALID },
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800357};
358
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600359static amd_bios_entry amd_bios_table[] = {
Marshall Dawson0581bf62019-09-25 11:03:53 -0600360 { .type = AMD_BIOS_APCB, .inst = 0, .level = BDT_BOTH },
361 { .type = AMD_BIOS_APCB, .inst = 1, .level = BDT_BOTH },
362 { .type = AMD_BIOS_APCB, .inst = 2, .level = BDT_BOTH },
363 { .type = AMD_BIOS_APCB, .inst = 3, .level = BDT_BOTH },
364 { .type = AMD_BIOS_APCB, .inst = 4, .level = BDT_BOTH },
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600365 { .type = AMD_BIOS_APCB_BK, .level = BDT_BOTH },
366 { .type = AMD_BIOS_APOB, .level = BDT_BOTH },
367 { .type = AMD_BIOS_BIN,
368 .reset = 1, .copy = 1, .zlib = 1, .level = BDT_BOTH },
369 { .type = AMD_BIOS_APOB_NV, .level = BDT_LVL2 },
370 { .type = AMD_BIOS_PMUI, .inst = 1, .subpr = 0, .level = BDT_BOTH },
371 { .type = AMD_BIOS_PMUD, .inst = 1, .subpr = 0, .level = BDT_BOTH },
372 { .type = AMD_BIOS_PMUI, .inst = 4, .subpr = 0, .level = BDT_BOTH },
373 { .type = AMD_BIOS_PMUD, .inst = 4, .subpr = 0, .level = BDT_BOTH },
374 { .type = AMD_BIOS_PMUI, .inst = 1, .subpr = 1, .level = BDT_BOTH },
375 { .type = AMD_BIOS_PMUD, .inst = 1, .subpr = 1, .level = BDT_BOTH },
376 { .type = AMD_BIOS_PMUI, .inst = 4, .subpr = 1, .level = BDT_BOTH },
377 { .type = AMD_BIOS_PMUD, .inst = 4, .subpr = 1, .level = BDT_BOTH },
378 { .type = AMD_BIOS_UCODE, .inst = 0, .level = BDT_LVL2 },
379 { .type = AMD_BIOS_UCODE, .inst = 1, .level = BDT_LVL2 },
380 { .type = AMD_BIOS_UCODE, .inst = 2, .level = BDT_LVL2 },
381 { .type = AMD_BIOS_MP2_CFG, .level = BDT_LVL2 },
382 { .type = AMD_BIOS_INVALID },
383};
384
Marshall Dawson239286c2019-02-23 16:42:46 -0700385typedef struct _embedded_firmware {
386 uint32_t signature; /* 0x55aa55aa */
387 uint32_t imc_entry;
388 uint32_t gec_entry;
389 uint32_t xhci_entry;
390 uint32_t psp_entry;
391 uint32_t comboable;
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600392 uint32_t bios0_entry; /* todo: add way to select correct entry */
393 uint32_t bios1_entry;
Marshall Dawson94f24922019-09-28 08:49:09 -0600394 uint32_t bios2_entry;
395 uint32_t reserved[0x2c]; /* 0x24 - 0x4f */
Marshall Dawson239286c2019-02-23 16:42:46 -0700396} __attribute__((packed, aligned(16))) embedded_firmware;
397
398typedef struct _psp_directory_header {
399 uint32_t cookie;
400 uint32_t checksum;
401 uint32_t num_entries;
402 uint32_t reserved;
403} __attribute__((packed, aligned(16))) psp_directory_header;
404
405typedef struct _psp_directory_entry {
Marshall Dawsondbae6322019-03-04 10:31:03 -0700406 uint8_t type;
407 uint8_t subprog;
408 uint16_t rsvd;
Marshall Dawson239286c2019-02-23 16:42:46 -0700409 uint32_t size;
410 uint64_t addr; /* or a value in some cases */
411} __attribute__((packed)) psp_directory_entry;
412
413typedef struct _psp_directory_table {
414 psp_directory_header header;
415 psp_directory_entry entries[];
416} __attribute__((packed)) psp_directory_table;
417
Marshall Dawson2794a862019-03-04 16:53:15 -0700418#define MAX_PSP_ENTRIES 0x1f
419
Marshall Dawson239286c2019-02-23 16:42:46 -0700420typedef struct _psp_combo_header {
421 uint32_t cookie;
422 uint32_t checksum;
423 uint32_t num_entries;
424 uint32_t lookup;
425 uint64_t reserved[2];
426} __attribute__((packed, aligned(16))) psp_combo_header;
427
428typedef struct _psp_combo_entry {
429 uint32_t id_sel;
430 uint32_t id;
431 uint64_t lvl2_addr;
432} __attribute__((packed)) psp_combo_entry;
433
434typedef struct _psp_combo_directory {
435 psp_combo_header header;
436 psp_combo_entry entries[];
437} __attribute__((packed)) psp_combo_directory;
438
Marshall Dawson2794a862019-03-04 16:53:15 -0700439#define MAX_COMBO_ENTRIES 1
440
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600441typedef struct _bios_directory_hdr {
442 uint32_t cookie;
443 uint32_t checksum;
444 uint32_t num_entries;
445 uint32_t reserved;
446} __attribute__((packed, aligned(16))) bios_directory_hdr;
447
448typedef struct _bios_directory_entry {
449 uint8_t type;
450 uint8_t region_type;
451 int reset:1;
452 int copy:1;
453 int ro:1;
454 int compressed:1;
455 int inst:4;
456 uint8_t subprog; /* b[7:3] reserved */
457 uint32_t size;
458 uint64_t source;
459 uint64_t dest;
460} __attribute__((packed)) bios_directory_entry;
461
462typedef struct _bios_directory_table {
463 bios_directory_hdr header;
464 bios_directory_entry entries[];
465} bios_directory_table;
466
467#define MAX_BIOS_ENTRIES 0x1f
468
Marshall Dawson2794a862019-03-04 16:53:15 -0700469typedef struct _context {
470 char *rom; /* target buffer, size of flash device */
471 uint32_t rom_size; /* size of flash device */
472 uint32_t current; /* pointer within flash & proxy buffer */
473} context;
474
475#define RUN_BASE(ctx) (0xFFFFFFFF - (ctx).rom_size + 1)
476#define RUN_OFFSET(ctx, offset) (RUN_BASE(ctx) + (offset))
477#define RUN_CURRENT(ctx) RUN_OFFSET((ctx), (ctx).current)
478#define BUFF_OFFSET(ctx, offset) ((void *)((ctx).rom + (offset)))
479#define BUFF_CURRENT(ctx) BUFF_OFFSET((ctx), (ctx).current)
480#define BUFF_TO_RUN(ctx, ptr) RUN_OFFSET((ctx), ((char *)(ptr) - (ctx).rom))
481#define BUFF_ROOM(ctx) ((ctx).rom_size - (ctx).current)
482
Marshall Dawson24f73d42019-04-01 10:48:43 -0600483static void *new_psp_dir(context *ctx, int multi)
Marshall Dawson2794a862019-03-04 16:53:15 -0700484{
485 void *ptr;
486
Marshall Dawson24f73d42019-04-01 10:48:43 -0600487 /*
488 * Force both onto boundary when multi. Primary table is after
489 * updatable table, so alignment ensures primary can stay intact
490 * if secondary is reprogrammed.
491 */
492 if (multi)
493 ctx->current = ALIGN(ctx->current, TABLE_ERASE_ALIGNMENT);
494 else
495 ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT);
496
Marshall Dawson2794a862019-03-04 16:53:15 -0700497 ptr = BUFF_CURRENT(*ctx);
498 ctx->current += sizeof(psp_directory_header)
499 + MAX_PSP_ENTRIES * sizeof(psp_directory_entry);
500 return ptr;
501}
502
Martin Rothec933132019-07-13 20:03:34 -0600503#if PSP_COMBO
Marshall Dawson2794a862019-03-04 16:53:15 -0700504static void *new_combo_dir(context *ctx)
505{
506 void *ptr;
507
508 ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT);
509 ptr = BUFF_CURRENT(*ctx);
510 ctx->current += sizeof(psp_combo_header)
511 + MAX_COMBO_ENTRIES * sizeof(psp_combo_entry);
512 return ptr;
513}
Martin Rothec933132019-07-13 20:03:34 -0600514#endif
Marshall Dawson2794a862019-03-04 16:53:15 -0700515
Marshall Dawsona378c222019-03-04 16:52:07 -0700516static void fill_dir_header(void *directory, uint32_t count, uint32_t cookie)
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800517{
Marshall Dawson24f73d42019-04-01 10:48:43 -0600518 psp_combo_directory *cdir = directory;
519 psp_directory_table *dir = directory;
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600520 bios_directory_table *bdir = directory;
Marshall Dawson24f73d42019-04-01 10:48:43 -0600521
522 if (!count)
523 return;
524
525 switch (cookie) {
526 case PSP2_COOKIE:
Marshall Dawsona378c222019-03-04 16:52:07 -0700527 /* caller is responsible for lookup mode */
Marshall Dawsona378c222019-03-04 16:52:07 -0700528 cdir->header.cookie = cookie;
529 cdir->header.num_entries = count;
530 cdir->header.reserved[0] = 0;
531 cdir->header.reserved[1] = 0;
532 /* checksum everything that comes after the Checksum field */
533 cdir->header.checksum = fletcher32(&cdir->header.num_entries,
534 count * sizeof(psp_combo_entry)
535 + sizeof(cdir->header.num_entries)
536 + sizeof(cdir->header.lookup)
537 + 2 * sizeof(cdir->header.reserved[0]));
Marshall Dawson24f73d42019-04-01 10:48:43 -0600538 break;
539 case PSP_COOKIE:
540 case PSPL2_COOKIE:
Marshall Dawsona378c222019-03-04 16:52:07 -0700541 dir->header.cookie = cookie;
542 dir->header.num_entries = count;
543 dir->header.reserved = 0;
544 /* checksum everything that comes after the Checksum field */
545 dir->header.checksum = fletcher32(&dir->header.num_entries,
Marshall Dawson8a45a4d2019-02-24 07:18:44 -0700546 count * sizeof(psp_directory_entry)
Marshall Dawsona378c222019-03-04 16:52:07 -0700547 + sizeof(dir->header.num_entries)
548 + sizeof(dir->header.reserved));
Marshall Dawson24f73d42019-04-01 10:48:43 -0600549 break;
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600550 case BDT1_COOKIE:
551 case BDT2_COOKIE:
552 bdir->header.cookie = cookie;
553 bdir->header.num_entries = count;
554 bdir->header.reserved = 0;
555 /* checksum everything that comes after the Checksum field */
556 bdir->header.checksum = fletcher32(&bdir->header.num_entries,
557 count * sizeof(bios_directory_entry)
558 + sizeof(bdir->header.num_entries)
559 + sizeof(bdir->header.reserved));
560 break;
Marshall Dawsona378c222019-03-04 16:52:07 -0700561 }
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800562}
563
Marshall Dawson8e0dca02019-02-27 18:40:49 -0700564static ssize_t copy_blob(void *dest, const char *src_file, size_t room)
565{
566 int fd;
567 struct stat fd_stat;
568 ssize_t bytes;
569
570 fd = open(src_file, O_RDONLY);
571 if (fd < 0) {
572 printf("Error: %s\n", strerror(errno));
573 return -1;
574 }
575
576 if (fstat(fd, &fd_stat)) {
577 printf("fstat error: %s\n", strerror(errno));
Jacob Garber967f8622019-07-02 10:35:10 -0600578 close(fd);
Marshall Dawson8e0dca02019-02-27 18:40:49 -0700579 return -2;
580 }
581
582 if (fd_stat.st_size > room) {
583 printf("Error: %s will not fit. Exiting.\n", src_file);
Jacob Garber967f8622019-07-02 10:35:10 -0600584 close(fd);
Marshall Dawson8e0dca02019-02-27 18:40:49 -0700585 return -3;
586 }
587
588 bytes = read(fd, dest, (size_t)fd_stat.st_size);
589 close(fd);
590 if (bytes != (ssize_t)fd_stat.st_size) {
591 printf("Error while reading %s\n", src_file);
592 return -4;
593 }
594
595 return bytes;
596}
597
Marshall Dawson2794a862019-03-04 16:53:15 -0700598static void integrate_firmwares(context *ctx,
Marshall Dawson239286c2019-02-23 16:42:46 -0700599 embedded_firmware *romsig,
Marshall Dawson2794a862019-03-04 16:53:15 -0700600 amd_fw_entry *fw_table)
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800601{
Richard Spiegel137484d2018-01-17 10:23:19 -0700602 ssize_t bytes;
zbaoc3a08a92016-03-02 14:47:27 +0800603 int i;
Marshall Dawson2794a862019-03-04 16:53:15 -0700604
605 ctx->current += sizeof(embedded_firmware);
606 ctx->current = ALIGN(ctx->current, BLOB_ALIGNMENT);
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800607
Martin Rothcd15bc82016-11-08 11:34:02 -0700608 for (i = 0; fw_table[i].type != AMD_FW_INVALID; i++) {
zbaoc3a08a92016-03-02 14:47:27 +0800609 if (fw_table[i].filename != NULL) {
zbaoc3a08a92016-03-02 14:47:27 +0800610 switch (fw_table[i].type) {
611 case AMD_FW_IMC:
Marshall Dawson2794a862019-03-04 16:53:15 -0700612 ctx->current = ALIGN(ctx->current, 0x10000U);
613 romsig->imc_entry = RUN_CURRENT(*ctx);
zbaoc3a08a92016-03-02 14:47:27 +0800614 break;
615 case AMD_FW_GEC:
Marshall Dawson2794a862019-03-04 16:53:15 -0700616 romsig->gec_entry = RUN_CURRENT(*ctx);
zbaoc3a08a92016-03-02 14:47:27 +0800617 break;
618 case AMD_FW_XHCI:
Marshall Dawson2794a862019-03-04 16:53:15 -0700619 romsig->xhci_entry = RUN_CURRENT(*ctx);
zbaoc3a08a92016-03-02 14:47:27 +0800620 break;
621 default:
622 /* Error */
623 break;
624 }
625
Marshall Dawson2794a862019-03-04 16:53:15 -0700626 bytes = copy_blob(BUFF_CURRENT(*ctx),
627 fw_table[i].filename, BUFF_ROOM(*ctx));
Marshall Dawson02bd7732019-03-13 14:43:17 -0600628 if (bytes < 0) {
Marshall Dawson2794a862019-03-04 16:53:15 -0700629 free(ctx->rom);
Martin Roth60f15512016-11-08 09:55:01 -0700630 exit(1);
631 }
632
Marshall Dawson2794a862019-03-04 16:53:15 -0700633 ctx->current = ALIGN(ctx->current + bytes,
634 BLOB_ALIGNMENT);
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800635 }
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800636 }
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800637}
638
Marshall Dawson2794a862019-03-04 16:53:15 -0700639static void integrate_psp_firmwares(context *ctx,
Marshall Dawson239286c2019-02-23 16:42:46 -0700640 psp_directory_table *pspdir,
Marshall Dawson24f73d42019-04-01 10:48:43 -0600641 psp_directory_table *pspdir2,
642 amd_fw_entry *fw_table,
643 uint32_t cookie)
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800644{
Richard Spiegel137484d2018-01-17 10:23:19 -0700645 ssize_t bytes;
Marshall Dawsonc38c0c92019-02-23 16:41:35 -0700646 unsigned int i, count;
Marshall Dawson24f73d42019-04-01 10:48:43 -0600647 int level;
648
649 /* This function can create a primary table, a secondary table, or a
650 * flattened table which contains all applicable types. These if-else
651 * statements infer what the caller intended. If a 2nd-level cookie
652 * is passed, clearly a 2nd-level table is intended. However, a
653 * 1st-level cookie may indicate level 1 or flattened. If the caller
654 * passes a pointer to a 2nd-level table, then assume not flat.
655 */
656 if (cookie == PSPL2_COOKIE)
657 level = PSP_LVL2;
658 else if (pspdir2)
659 level = PSP_LVL1;
660 else
661 level = PSP_BOTH;
Marshall Dawson2794a862019-03-04 16:53:15 -0700662
663 ctx->current = ALIGN(ctx->current, BLOB_ALIGNMENT);
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800664
Marshall Dawsonc38c0c92019-02-23 16:41:35 -0700665 for (i = 0, count = 0; fw_table[i].type != AMD_FW_INVALID; i++) {
Marshall Dawson24f73d42019-04-01 10:48:43 -0600666 if (!(fw_table[i].level & level))
667 continue;
668
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600669 if (fw_table[i].type == AMD_TOKEN_UNLOCK) {
670 if (!fw_table[i].other)
671 continue;
672 ctx->current = ALIGN(ctx->current, ERASE_ALIGNMENT);
673 pspdir->entries[count].type = fw_table[i].type;
674 pspdir->entries[count].size = 4096; /* TODO: doc? */
675 pspdir->entries[count].addr = RUN_CURRENT(*ctx);
676 pspdir->entries[count].subprog = fw_table[i].subprog;
677 pspdir->entries[count].rsvd = 0;
678 ctx->current = ALIGN(ctx->current + 4096, 0x100U);
679 count++;
680 } else if (fw_table[i].type == AMD_PSP_FUSE_CHAIN) {
Marshall Dawson239286c2019-02-23 16:42:46 -0700681 pspdir->entries[count].type = fw_table[i].type;
Marshall Dawsondbae6322019-03-04 10:31:03 -0700682 pspdir->entries[count].subprog = fw_table[i].subprog;
683 pspdir->entries[count].rsvd = 0;
Marshall Dawson239286c2019-02-23 16:42:46 -0700684 pspdir->entries[count].size = 0xFFFFFFFF;
Marshall Dawsonef79fcc2019-04-01 10:16:41 -0600685 pspdir->entries[count].addr = fw_table[i].other;
Marshall Dawsonc38c0c92019-02-23 16:41:35 -0700686 count++;
Marshall Dawson7c1e1422019-04-11 09:44:43 -0600687 } else if (fw_table[i].type == AMD_FW_PSP_NVRAM) {
688 if (fw_table[i].filename == NULL)
689 continue;
690 /* TODO: Add a way to reserve for NVRAM without
691 * requiring a filename. This isn't a feature used
692 * by coreboot systems, so priority is very low.
693 */
694 ctx->current = ALIGN(ctx->current, ERASE_ALIGNMENT);
695 bytes = copy_blob(BUFF_CURRENT(*ctx),
696 fw_table[i].filename, BUFF_ROOM(*ctx));
697 if (bytes <= 0) {
698 free(ctx->rom);
699 exit(1);
700 }
701
702 pspdir->entries[count].type = fw_table[i].type;
703 pspdir->entries[count].subprog = fw_table[i].subprog;
704 pspdir->entries[count].rsvd = 0;
705 pspdir->entries[count].size = ALIGN(bytes,
706 ERASE_ALIGNMENT);
707 pspdir->entries[count].addr = RUN_CURRENT(*ctx);
708
709 ctx->current = ALIGN(ctx->current + bytes,
710 BLOB_ERASE_ALIGNMENT);
711 count++;
zbaoc3a08a92016-03-02 14:47:27 +0800712 } else if (fw_table[i].filename != NULL) {
Marshall Dawson2794a862019-03-04 16:53:15 -0700713 bytes = copy_blob(BUFF_CURRENT(*ctx),
714 fw_table[i].filename, BUFF_ROOM(*ctx));
Marshall Dawson02bd7732019-03-13 14:43:17 -0600715 if (bytes < 0) {
Marshall Dawson2794a862019-03-04 16:53:15 -0700716 free(ctx->rom);
Marshall Dawson8e0dca02019-02-27 18:40:49 -0700717 exit(1);
718 }
719
Marshall Dawson239286c2019-02-23 16:42:46 -0700720 pspdir->entries[count].type = fw_table[i].type;
Marshall Dawsondbae6322019-03-04 10:31:03 -0700721 pspdir->entries[count].subprog = fw_table[i].subprog;
722 pspdir->entries[count].rsvd = 0;
Marshall Dawson8e0dca02019-02-27 18:40:49 -0700723 pspdir->entries[count].size = (uint32_t)bytes;
Marshall Dawson2794a862019-03-04 16:53:15 -0700724 pspdir->entries[count].addr = RUN_CURRENT(*ctx);
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800725
Marshall Dawson2794a862019-03-04 16:53:15 -0700726 ctx->current = ALIGN(ctx->current + bytes,
727 BLOB_ALIGNMENT);
Marshall Dawsonc38c0c92019-02-23 16:41:35 -0700728 count++;
zbaoc3a08a92016-03-02 14:47:27 +0800729 } else {
730 /* This APU doesn't have this firmware. */
731 }
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800732 }
Marshall Dawson2794a862019-03-04 16:53:15 -0700733
Marshall Dawson24f73d42019-04-01 10:48:43 -0600734 if (pspdir2) {
735 pspdir->entries[count].type = AMD_FW_L2_PTR;
736 pspdir->entries[count].subprog = 0;
737 pspdir->entries[count].rsvd = 0;
738 pspdir->entries[count].size = sizeof(pspdir2->header)
739 + pspdir2->header.num_entries
740 * sizeof(psp_directory_entry);
741
742 pspdir->entries[count].addr = BUFF_TO_RUN(*ctx, pspdir2);
743 count++;
744 }
745
Marshall Dawson2794a862019-03-04 16:53:15 -0700746 if (count > MAX_PSP_ENTRIES) {
747 printf("Error: PSP entries exceed max allowed items\n");
748 free(ctx->rom);
749 exit(1);
750 }
751
Marshall Dawson24f73d42019-04-01 10:48:43 -0600752 fill_dir_header(pspdir, count, cookie);
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800753}
754
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600755static void *new_bios_dir(context *ctx, int multi)
756{
757 void *ptr;
758
759 /*
760 * Force both onto boundary when multi. Primary table is after
761 * updatable table, so alignment ensures primary can stay intact
762 * if secondary is reprogrammed.
763 */
764 if (multi)
765 ctx->current = ALIGN(ctx->current, TABLE_ERASE_ALIGNMENT);
766 else
767 ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT);
768 ptr = BUFF_CURRENT(*ctx);
769 ctx->current += sizeof(bios_directory_hdr)
770 + MAX_BIOS_ENTRIES * sizeof(bios_directory_entry);
771 return ptr;
772}
773
774static int locate_bdt2_bios(bios_directory_table *level2,
775 uint64_t *source, uint32_t *size)
776{
777 int i;
778
779 *source = 0;
780 *size = 0;
781 if (!level2)
782 return 0;
783
784 for (i = 0 ; i < level2->header.num_entries ; i++) {
785 if (level2->entries[i].type == AMD_BIOS_BIN) {
786 *source = level2->entries[i].source;
787 *size = level2->entries[i].size;
788 return 1;
789 }
790 }
791 return 0;
792}
793
794static int have_bios_tables(amd_bios_entry *table)
795{
796 int i;
797
798 for (i = 0 ; table[i].type != AMD_BIOS_INVALID; i++) {
799 if (table[i].level & BDT_LVL1 && table[i].filename)
800 return 1;
801 }
802 return 0;
803}
804
805static void integrate_bios_firmwares(context *ctx,
806 bios_directory_table *biosdir,
807 bios_directory_table *biosdir2,
808 amd_bios_entry *fw_table,
809 uint32_t cookie)
810{
811 ssize_t bytes;
Martin Rothec933132019-07-13 20:03:34 -0600812 unsigned int i, count;
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600813 int level;
814
815 /* This function can create a primary table, a secondary table, or a
816 * flattened table which contains all applicable types. These if-else
817 * statements infer what the caller intended. If a 2nd-level cookie
818 * is passed, clearly a 2nd-level table is intended. However, a
819 * 1st-level cookie may indicate level 1 or flattened. If the caller
820 * passes a pointer to a 2nd-level table, then assume not flat.
821 */
822 if (cookie == BDT2_COOKIE)
823 level = BDT_LVL2;
824 else if (biosdir2)
825 level = BDT_LVL1;
826 else
827 level = BDT_BOTH;
828
829 ctx->current = ALIGN(ctx->current, BLOB_ALIGNMENT);
830
831 for (i = 0, count = 0; fw_table[i].type != AMD_BIOS_INVALID; i++) {
832 if (!(fw_table[i].level & level))
833 continue;
834 if (fw_table[i].filename == NULL && (
835 fw_table[i].type != AMD_BIOS_APOB &&
836 fw_table[i].type != AMD_BIOS_APOB_NV &&
837 fw_table[i].type != AMD_BIOS_L2_PTR &&
838 fw_table[i].type != AMD_BIOS_BIN))
839 continue;
840 /* APOB_NV needs a size, else no S3 and skip item */
841 if (fw_table[i].type == AMD_BIOS_APOB_NV && !fw_table[i].size)
842 continue;
843
844 /* BIOS Directory items may have additional requirements */
845
846 /* APOB_NV must have a size if it has a source */
847 if (fw_table[i].type == AMD_BIOS_APOB_NV && fw_table[i].src) {
848 if (!fw_table[i].size) {
849 printf("Error: APOB NV address provided, but no size\n");
850 free(ctx->rom);
851 exit(1);
852 }
853 }
854
855 /* APOB_DATA needs destination */
856 if (fw_table[i].type == AMD_BIOS_APOB && !fw_table[i].dest) {
857 printf("Error: APOB destination not provided\n");
858 free(ctx->rom);
859 exit(1);
860 }
861
862 /* BIOS binary must have destination and uncompressed size. If
863 * no filename given, then user must provide a source address.
864 */
865 if (fw_table[i].type == AMD_BIOS_BIN) {
866 if (!fw_table[i].dest || !fw_table[i].size) {
867 printf("Error: BIOS binary destination and uncompressed size are required\n");
868 free(ctx->rom);
869 exit(1);
870 }
871 if (!fw_table[i].filename && !fw_table[i].src) {
872 printf("Error: BIOS binary assumed outside amdfw.rom but no source address given\n");
873 free(ctx->rom);
874 exit(1);
875 }
876 }
877
878 biosdir->entries[count].type = fw_table[i].type;
879 biosdir->entries[count].region_type = fw_table[i].region_type;
880 biosdir->entries[count].dest = fw_table[i].dest ?
881 fw_table[i].dest : (uint64_t)-1;
882 biosdir->entries[count].reset = fw_table[i].reset;
883 biosdir->entries[count].copy = fw_table[i].copy;
884 biosdir->entries[count].ro = fw_table[i].ro;
885 biosdir->entries[count].compressed = fw_table[i].zlib;
886 biosdir->entries[count].inst = fw_table[i].inst;
887 biosdir->entries[count].subprog = fw_table[i].subpr;
888
889 switch (fw_table[i].type) {
890 case AMD_BIOS_APOB:
891 biosdir->entries[count].size = fw_table[i].size;
892 biosdir->entries[count].source = fw_table[i].src;
893 break;
894 case AMD_BIOS_APOB_NV:
895 if (fw_table[i].src) {
896 /* If source is given, use that and its size */
897 biosdir->entries[count].source = fw_table[i].src;
898 biosdir->entries[count].size = fw_table[i].size;
899 } else {
900 /* Else reserve size bytes within amdfw.rom */
901 ctx->current = ALIGN(ctx->current, ERASE_ALIGNMENT);
902 biosdir->entries[count].source = RUN_CURRENT(*ctx);
903 biosdir->entries[count].size = ALIGN(
904 fw_table[i].size, ERASE_ALIGNMENT);
905 memset(BUFF_CURRENT(*ctx), 0xff,
906 biosdir->entries[count].size);
907 ctx->current = ctx->current
908 + biosdir->entries[count].size;
909 }
910 break;
911 case AMD_BIOS_BIN:
912 /* Don't make a 2nd copy, point to the same one */
913 if (level == BDT_LVL1 && locate_bdt2_bios(biosdir2,
914 &biosdir->entries[count].source,
915 &biosdir->entries[count].size))
916 break;
917
918 /* level 2, or level 1 and no copy found in level 2 */
919 biosdir->entries[count].source = fw_table[i].src;
920 biosdir->entries[count].dest = fw_table[i].dest;
921 biosdir->entries[count].size = fw_table[i].size;
922
923 if (!fw_table[i].filename)
924 break;
925
926 bytes = copy_blob(BUFF_CURRENT(*ctx),
927 fw_table[i].filename, BUFF_ROOM(*ctx));
928 if (bytes <= 0) {
929 free(ctx->rom);
930 exit(1);
931 }
932
933 biosdir->entries[count].source = RUN_CURRENT(*ctx);
934
935 ctx->current = ALIGN(ctx->current + bytes, 0x100U);
936 break;
937 default: /* everything else is copied from input */
938 if (fw_table[i].type == AMD_BIOS_APCB ||
939 fw_table[i].type == AMD_BIOS_APCB_BK)
940 ctx->current = ALIGN(
941 ctx->current, ERASE_ALIGNMENT);
942
943 bytes = copy_blob(BUFF_CURRENT(*ctx),
944 fw_table[i].filename, BUFF_ROOM(*ctx));
945 if (bytes <= 0) {
946 free(ctx->rom);
947 exit(1);
948 }
949
950 biosdir->entries[count].size = (uint32_t)bytes;
951 biosdir->entries[count].source = RUN_CURRENT(*ctx);
952
953 ctx->current = ALIGN(ctx->current + bytes, 0x100U);
954 break;
955 }
956
957 count++;
958 }
959
960 if (biosdir2) {
961 biosdir->entries[count].type = AMD_BIOS_L2_PTR;
962 biosdir->entries[count].size =
963 + MAX_BIOS_ENTRIES
964 * sizeof(bios_directory_entry);
965 biosdir->entries[count].source =
966 BUFF_TO_RUN(*ctx, biosdir2);
967 biosdir->entries[count].subprog = 0;
968 biosdir->entries[count].inst = 0;
969 biosdir->entries[count].copy = 0;
970 biosdir->entries[count].compressed = 0;
971 biosdir->entries[count].dest = -1;
972 biosdir->entries[count].reset = 0;
973 biosdir->entries[count].ro = 0;
974 count++;
975 }
976
977 if (count > MAX_BIOS_ENTRIES) {
978 printf("Error: BIOS entries exceeds max allowed items\n");
979 free(ctx->rom);
980 exit(1);
981 }
982
983 fill_dir_header(biosdir, count, cookie);
984}
Martin Rothd3ce8c82019-07-13 20:13:07 -0600985// Unused values: CDEPqR
986static const char *optstring = "x:i:g:AMS:p:b:s:r:k:c:n:d:t:u:w:m:T:z:J:B:K:L:Y:N:UW:I:a:Q:V:e:v:j:y:G:O:X:F:H:o:f:l:hZ:";
Marc Jones90099b62016-09-20 21:05:45 -0600987
Zheng Bao9c7ff7b2015-11-17 22:57:39 +0800988static struct option long_options[] = {
Marshall Dawsonf4b9b412017-03-17 16:30:51 -0600989 {"xhci", required_argument, 0, 'x' },
990 {"imc", required_argument, 0, 'i' },
991 {"gec", required_argument, 0, 'g' },
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -0600992 /* PSP Directory Table items */
Marshall Dawson67d868d2019-02-28 11:43:40 -0700993 {"combo-capable", no_argument, 0, 'A' },
Marshall Dawson24f73d42019-04-01 10:48:43 -0600994 {"multilevel", no_argument, 0, 'M' },
Marshall Dawsondbae6322019-03-04 10:31:03 -0700995 {"subprogram", required_argument, 0, 'S' },
Marshall Dawsonf4b9b412017-03-17 16:30:51 -0600996 {"pubkey", required_argument, 0, 'p' },
997 {"bootloader", required_argument, 0, 'b' },
998 {"smufirmware", required_argument, 0, 's' },
999 {"recovery", required_argument, 0, 'r' },
1000 {"rtmpubkey", required_argument, 0, 'k' },
1001 {"secureos", required_argument, 0, 'c' },
1002 {"nvram", required_argument, 0, 'n' },
1003 {"securedebug", required_argument, 0, 'd' },
1004 {"trustlets", required_argument, 0, 't' },
1005 {"trustletkey", required_argument, 0, 'u' },
1006 {"smufirmware2", required_argument, 0, 'w' },
1007 {"smuscs", required_argument, 0, 'm' },
Marshall Dawsonef79fcc2019-04-01 10:16:41 -06001008 {"soft-fuse", required_argument, 0, 'T' },
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001009 {"abl-image", required_argument, 0, 'z' },
1010 {"sec-gasket", required_argument, 0, 'J' },
1011 {"mp2-fw", required_argument, 0, 'B' },
1012 {"drv-entry-pts", required_argument, 0, 'K' },
1013 {"ikek", required_argument, 0, 'L' },
1014 {"s0i3drv", required_argument, 0, 'Y' },
1015 {"secdebug", required_argument, 0, 'N' },
1016 {"token-unlock", no_argument, 0, 'U' },
1017 {"whitelist", required_argument, 0, 'W' },
Martin Rothd3ce8c82019-07-13 20:13:07 -06001018 {"verstage", required_argument, 0, 'Z' },
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001019 /* BIOS Directory Table items */
1020 {"instance", required_argument, 0, 'I' },
1021 {"apcb", required_argument, 0, 'a' },
1022 {"apob-base", required_argument, 0, 'Q' },
1023 {"bios-bin", required_argument, 0, 'V' },
1024 {"bios-bin-src", required_argument, 0, 'e' },
1025 {"bios-bin-dest", required_argument, 0, 'v' },
1026 {"bios-uncomp-size", required_argument, 0, 'j' },
1027 {"pmu-inst", required_argument, 0, 'y' },
1028 {"pmu-data", required_argument, 0, 'G' },
1029 {"ucode", required_argument, 0, 'O' },
1030 {"mp2-config", required_argument, 0, 'X' },
1031 {"apob-nv-base", required_argument, 0, 'F' },
1032 {"apob-nv-size", required_argument, 0, 'H' },
1033 /* other */
Marshall Dawsonf4b9b412017-03-17 16:30:51 -06001034 {"output", required_argument, 0, 'o' },
1035 {"flashsize", required_argument, 0, 'f' },
Martin Roth0d3b1182017-10-03 14:16:04 -06001036 {"location", required_argument, 0, 'l' },
Marshall Dawsonf4b9b412017-03-17 16:30:51 -06001037 {"help", no_argument, 0, 'h' },
Marshall Dawsonf4b9b412017-03-17 16:30:51 -06001038 {NULL, 0, 0, 0 }
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001039};
1040
Marshall Dawsonef79fcc2019-04-01 10:16:41 -06001041static void register_fw_fuse(char *str)
1042{
1043 int i;
1044
1045 for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) {
1046 if (amd_psp_fw_table[i].type != AMD_PSP_FUSE_CHAIN)
1047 continue;
1048
1049 amd_psp_fw_table[i].other = strtoull(str, NULL, 16);
1050 return;
1051 }
1052}
1053
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001054static void register_fw_token_unlock(void)
1055{
1056 int i;
1057
1058 for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) {
1059 if (amd_psp_fw_table[i].type != AMD_TOKEN_UNLOCK)
1060 continue;
1061
1062 amd_psp_fw_table[i].other = 1;
1063 return;
1064 }
1065}
1066
Marshall Dawsondbae6322019-03-04 10:31:03 -07001067static void register_fw_filename(amd_fw_type type, uint8_t sub, char filename[])
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001068{
Martin Roth8806f7f2016-11-08 10:44:18 -07001069 unsigned int i;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001070
Martin Rothcd15bc82016-11-08 11:34:02 -07001071 for (i = 0; i < sizeof(amd_fw_table) / sizeof(amd_fw_entry); i++) {
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001072 if (amd_fw_table[i].type == type) {
1073 amd_fw_table[i].filename = filename;
1074 return;
1075 }
1076 }
1077
Marshall Dawson0e02ce82019-03-04 16:50:37 -07001078 for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) {
Marshall Dawsondbae6322019-03-04 10:31:03 -07001079 if (amd_psp_fw_table[i].type != type)
1080 continue;
1081
1082 if (amd_psp_fw_table[i].subprog == sub) {
Marshall Dawson0e02ce82019-03-04 16:50:37 -07001083 amd_psp_fw_table[i].filename = filename;
1084 return;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001085 }
1086 }
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001087}
1088
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001089static void register_bdt_data(amd_bios_type type, int sub, int ins, char name[])
1090{
1091 int i;
1092
1093 for (i = 0; i < sizeof(amd_bios_table) / sizeof(amd_bios_entry); i++) {
1094 if (amd_bios_table[i].type == type
1095 && amd_bios_table[i].inst == ins
1096 && amd_bios_table[i].subpr == sub) {
1097 amd_bios_table[i].filename = name;
1098 return;
1099 }
1100 }
1101}
1102
Martin Rothec933132019-07-13 20:03:34 -06001103static void register_fw_addr(amd_bios_type type, char *src_str,
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001104 char *dst_str, char *size_str)
1105{
1106 int i;
1107 for (i = 0; i < sizeof(amd_bios_table) / sizeof(amd_bios_entry); i++) {
1108 if (amd_bios_table[i].type != type)
1109 continue;
1110
1111 if (src_str)
1112 amd_bios_table[i].src = strtoull(src_str, NULL, 16);
1113 if (dst_str)
1114 amd_bios_table[i].dest = strtoull(dst_str, NULL, 16);
1115 if (size_str)
1116 amd_bios_table[i].size = strtoul(size_str, NULL, 16);
1117
1118 return;
1119 }
1120}
1121
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001122int main(int argc, char **argv)
1123{
Marshall Dawson0e02ce82019-03-04 16:50:37 -07001124 int c;
Martin Roth31d95a22016-11-08 11:22:12 -07001125 int retval = 0;
Martin Roth60f15512016-11-08 09:55:01 -07001126 char *tmp;
Martin Roth8806f7f2016-11-08 10:44:18 -07001127 char *rom = NULL;
Marshall Dawson239286c2019-02-23 16:42:46 -07001128 embedded_firmware *amd_romsig;
1129 psp_directory_table *pspdir;
Marshall Dawson67d868d2019-02-28 11:43:40 -07001130 int comboable = 0;
Marshall Dawsonef79fcc2019-04-01 10:16:41 -06001131 int fuse_defined = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001132 int targetfd;
Martin Roth8806f7f2016-11-08 10:44:18 -07001133 char *output = NULL;
Marshall Dawson2794a862019-03-04 16:53:15 -07001134 context ctx = {
1135 .rom_size = CONFIG_ROM_SIZE,
1136 };
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001137 /* Values cleared after each firmware or parameter, regardless if N/A */
1138 uint8_t sub = 0, instance = 0;
1139 int abl_image = 0;
Martin Roth0d3b1182017-10-03 14:16:04 -06001140 uint32_t dir_location = 0;
1141 uint32_t romsig_offset;
Martin Roth60f15512016-11-08 09:55:01 -07001142 uint32_t rom_base_address;
Marshall Dawson24f73d42019-04-01 10:48:43 -06001143 int multi = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001144
1145 while (1) {
1146 int optindex = 0;
1147
1148 c = getopt_long(argc, argv, optstring, long_options, &optindex);
1149
1150 if (c == -1)
1151 break;
1152
1153 switch (c) {
1154 case 'x':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001155 register_fw_filename(AMD_FW_XHCI, sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001156 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001157 break;
1158 case 'i':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001159 register_fw_filename(AMD_FW_IMC, sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001160 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001161 break;
1162 case 'g':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001163 register_fw_filename(AMD_FW_GEC, sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001164 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001165 break;
Marshall Dawson67d868d2019-02-28 11:43:40 -07001166 case 'A':
1167 comboable = 1;
1168 break;
Marshall Dawson24f73d42019-04-01 10:48:43 -06001169 case 'M':
1170 multi = 1;
1171 break;
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001172 case 'U':
1173 register_fw_token_unlock();
1174 sub = instance = 0;
1175 break;
Marshall Dawsondbae6322019-03-04 10:31:03 -07001176 case 'S':
1177 sub = (uint8_t)strtoul(optarg, &tmp, 16);
1178 break;
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001179 case 'I':
1180 instance = strtoul(optarg, &tmp, 16);
1181 break;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001182 case 'p':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001183 register_fw_filename(AMD_FW_PSP_PUBKEY, sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001184 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001185 break;
1186 case 'b':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001187 register_fw_filename(AMD_FW_PSP_BOOTLOADER,
1188 sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001189 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001190 break;
1191 case 's':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001192 register_fw_filename(AMD_FW_PSP_SMU_FIRMWARE,
1193 sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001194 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001195 break;
1196 case 'r':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001197 register_fw_filename(AMD_FW_PSP_RECOVERY, sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001198 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001199 break;
1200 case 'k':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001201 register_fw_filename(AMD_FW_PSP_RTM_PUBKEY,
1202 sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001203 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001204 break;
1205 case 'c':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001206 register_fw_filename(AMD_FW_PSP_SECURED_OS,
1207 sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001208 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001209 break;
1210 case 'n':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001211 register_fw_filename(AMD_FW_PSP_NVRAM, sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001212 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001213 break;
1214 case 'd':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001215 register_fw_filename(AMD_FW_PSP_SECURED_DEBUG,
1216 sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001217 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001218 break;
1219 case 't':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001220 register_fw_filename(AMD_FW_PSP_TRUSTLETS, sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001221 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001222 break;
1223 case 'u':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001224 register_fw_filename(AMD_FW_PSP_TRUSTLETKEY,
1225 sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001226 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001227 break;
1228 case 'w':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001229 register_fw_filename(AMD_FW_PSP_SMU_FIRMWARE2,
1230 sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001231 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001232 break;
1233 case 'm':
Marshall Dawsondbae6322019-03-04 10:31:03 -07001234 register_fw_filename(AMD_FW_PSP_SMUSCS, sub, optarg);
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001235 sub = instance = 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001236 break;
Marshall Dawsonef79fcc2019-04-01 10:16:41 -06001237 case 'T':
1238 register_fw_fuse(optarg);
1239 fuse_defined = 1;
1240 sub = 0;
1241 break;
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001242 case 'a':
1243 register_bdt_data(AMD_BIOS_APCB, sub, instance, optarg);
1244 register_bdt_data(AMD_BIOS_APCB_BK, sub,
1245 instance, optarg);
1246 sub = instance = 0;
1247 break;
1248 case 'Q':
1249 /* APOB destination */
1250 register_fw_addr(AMD_BIOS_APOB, 0, optarg, 0);
1251 sub = instance = 0;
1252 break;
1253 case 'F':
1254 /* APOB NV source */
1255 register_fw_addr(AMD_BIOS_APOB_NV, optarg, 0, 0);
1256 sub = instance = 0;
1257 break;
1258 case 'H':
1259 /* APOB NV size */
1260 register_fw_addr(AMD_BIOS_APOB_NV, 0, 0, optarg);
1261 sub = instance = 0;
1262 break;
1263 case 'V':
1264 register_bdt_data(AMD_BIOS_BIN, sub, instance, optarg);
1265 sub = instance = 0;
1266 break;
1267 case 'e':
1268 /* BIOS source */
1269 register_fw_addr(AMD_BIOS_BIN, optarg, 0, 0);
1270 sub = instance = 0;
1271 break;
1272 case 'v':
1273 /* BIOS destination */
1274 register_fw_addr(AMD_BIOS_BIN, 0, optarg, 0);
1275 sub = instance = 0;
1276 break;
1277 case 'j':
1278 /* BIOS destination size */
1279 register_fw_addr(AMD_BIOS_BIN, 0, 0, optarg);
1280 sub = instance = 0;
1281 break;
1282 case 'y':
1283 register_bdt_data(AMD_BIOS_PMUI, sub, instance, optarg);
1284 sub = instance = 0;
1285 break;
1286 case 'G':
1287 register_bdt_data(AMD_BIOS_PMUD, sub, instance, optarg);
1288 sub = instance = 0;
1289 break;
1290 case 'O':
1291 register_bdt_data(AMD_BIOS_UCODE, sub,
1292 instance, optarg);
1293 sub = instance = 0;
1294 break;
1295 case 'J':
1296 register_fw_filename(AMD_SEC_GASKET, sub, optarg);
1297 sub = instance = 0;
1298 break;
1299 case 'B':
1300 register_fw_filename(AMD_MP2_FW, sub, optarg);
1301 sub = instance = 0;
1302 break;
1303 case 'z':
1304 register_fw_filename(AMD_ABL0 + abl_image++,
1305 sub, optarg);
1306 sub = instance = 0;
1307 break;
1308 case 'X':
1309 register_bdt_data(AMD_BIOS_MP2_CFG, sub,
1310 instance, optarg);
1311 sub = instance = 0;
1312 break;
1313 case 'K':
1314 register_fw_filename(AMD_DRIVER_ENTRIES, sub, optarg);
1315 sub = instance = 0;
1316 break;
1317 case 'L':
1318 register_fw_filename(AMD_WRAPPED_IKEK, sub, optarg);
1319 sub = instance = 0;
1320 break;
1321 case 'Y':
1322 register_fw_filename(AMD_S0I3_DRIVER, sub, optarg);
1323 sub = instance = 0;
1324 break;
1325 case 'N':
1326 register_fw_filename(AMD_DEBUG_UNLOCK, sub, optarg);
1327 sub = instance = 0;
1328 break;
1329 case 'W':
1330 register_fw_filename(AMD_FW_PSP_WHITELIST, sub, optarg);
1331 sub = instance = 0;
1332 break;
Martin Rothd3ce8c82019-07-13 20:13:07 -06001333 case 'Z':
1334 register_fw_filename(AMD_FW_PSP_VERSTAGE, sub, optarg);
1335 sub = instance = 0;
1336 break;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001337 case 'o':
1338 output = optarg;
1339 break;
Martin Roth60f15512016-11-08 09:55:01 -07001340 case 'f':
Marshall Dawson2794a862019-03-04 16:53:15 -07001341 ctx.rom_size = (uint32_t)strtoul(optarg, &tmp, 16);
Martin Roth60f15512016-11-08 09:55:01 -07001342 if (*tmp != '\0') {
1343 printf("Error: ROM size specified"
1344 " incorrectly (%s)\n\n", optarg);
Martin Roth31d95a22016-11-08 11:22:12 -07001345 retval = 1;
Martin Roth60f15512016-11-08 09:55:01 -07001346 }
1347 break;
Martin Roth0d3b1182017-10-03 14:16:04 -06001348 case 'l':
1349 dir_location = (uint32_t)strtoul(optarg, &tmp, 16);
1350 if (*tmp != '\0') {
1351 printf("Error: Directory Location specified"
1352 " incorrectly (%s)\n\n", optarg);
1353 retval = 1;
1354 }
1355 break;
1356
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001357 case 'h':
1358 usage();
Martin Roth31d95a22016-11-08 11:22:12 -07001359 return 0;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001360 default:
1361 break;
1362 }
1363 }
1364
Marshall Dawsonef79fcc2019-04-01 10:16:41 -06001365 if (!fuse_defined)
1366 register_fw_fuse(DEFAULT_SOFT_FUSE_CHAIN);
1367
Martin Roth8806f7f2016-11-08 10:44:18 -07001368 if (!output) {
Martin Roth31d95a22016-11-08 11:22:12 -07001369 printf("Error: Output value is not specified.\n\n");
1370 retval = 1;
1371 }
1372
Marshall Dawson2794a862019-03-04 16:53:15 -07001373 if (ctx.rom_size % 1024 != 0) {
Martin Roth60f15512016-11-08 09:55:01 -07001374 printf("Error: ROM Size (%d bytes) should be a multiple of"
Marshall Dawson2794a862019-03-04 16:53:15 -07001375 " 1024 bytes.\n\n", ctx.rom_size);
Martin Roth31d95a22016-11-08 11:22:12 -07001376 retval = 1;
Martin Roth60f15512016-11-08 09:55:01 -07001377 }
1378
Marshall Dawson2794a862019-03-04 16:53:15 -07001379 if (ctx.rom_size < MIN_ROM_KB * 1024) {
Martin Roth31d95a22016-11-08 11:22:12 -07001380 printf("Error: ROM Size (%dKB) must be at least %dKB.\n\n",
Marshall Dawson2794a862019-03-04 16:53:15 -07001381 ctx.rom_size / 1024, MIN_ROM_KB);
Martin Roth31d95a22016-11-08 11:22:12 -07001382 retval = 1;
1383 }
1384
1385 if (retval) {
1386 usage();
1387 return retval;
Martin Roth60f15512016-11-08 09:55:01 -07001388 }
1389
Marshall Dawson2794a862019-03-04 16:53:15 -07001390 printf(" AMDFWTOOL Using ROM size of %dKB\n", ctx.rom_size / 1024);
Martin Roth60f15512016-11-08 09:55:01 -07001391
Marshall Dawson2794a862019-03-04 16:53:15 -07001392 rom_base_address = 0xFFFFFFFF - ctx.rom_size + 1;
Martin Roth0d3b1182017-10-03 14:16:04 -06001393 if (dir_location && (dir_location < rom_base_address)) {
1394 printf("Error: Directory location outside of ROM.\n\n");
1395 return 1;
1396 }
1397
1398 switch (dir_location) {
1399 case 0: /* Fall through */
1400 case 0xFFFA0000: /* Fall through */
1401 case 0xFFF20000: /* Fall through */
1402 case 0xFFE20000: /* Fall through */
1403 case 0xFFC20000: /* Fall through */
1404 case 0xFF820000: /* Fall through */
1405 case 0xFF020000: /* Fall through */
1406 break;
1407 default:
1408 printf("Error: Invalid Directory location.\n");
1409 printf(" Valid locations are 0xFFFA0000, 0xFFF20000,\n");
1410 printf(" 0xFFE20000, 0xFFC20000, 0xFF820000, 0xFF020000\n");
1411 return 1;
1412 }
1413
Marshall Dawson2794a862019-03-04 16:53:15 -07001414 ctx.rom = malloc(ctx.rom_size);
1415 if (!ctx.rom) {
1416 printf("Error: Failed to allocate memory\n");
Martin Roth31d95a22016-11-08 11:22:12 -07001417 return 1;
Marshall Dawson2794a862019-03-04 16:53:15 -07001418 }
1419 memset(ctx.rom, 0xFF, ctx.rom_size);
Martin Roth60f15512016-11-08 09:55:01 -07001420
Martin Roth0d3b1182017-10-03 14:16:04 -06001421 if (dir_location)
Marshall Dawson2794a862019-03-04 16:53:15 -07001422 romsig_offset = ctx.current = dir_location - rom_base_address;
Martin Roth0d3b1182017-10-03 14:16:04 -06001423 else
Marshall Dawson2794a862019-03-04 16:53:15 -07001424 romsig_offset = ctx.current = AMD_ROMSIG_OFFSET;
1425 printf(" AMDFWTOOL Using firmware directory location of 0x%08x\n",
1426 RUN_CURRENT(ctx));
Martin Roth0d3b1182017-10-03 14:16:04 -06001427
Marshall Dawson2794a862019-03-04 16:53:15 -07001428 amd_romsig = BUFF_OFFSET(ctx, romsig_offset);
Marshall Dawson239286c2019-02-23 16:42:46 -07001429 amd_romsig->signature = EMBEDDED_FW_SIGNATURE;
1430 amd_romsig->imc_entry = 0;
1431 amd_romsig->gec_entry = 0;
1432 amd_romsig->xhci_entry = 0;
Martin Roth60f15512016-11-08 09:55:01 -07001433
Marshall Dawson2794a862019-03-04 16:53:15 -07001434 integrate_firmwares(&ctx, amd_romsig, amd_fw_table);
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001435
Marshall Dawson2794a862019-03-04 16:53:15 -07001436 ctx.current = ALIGN(ctx.current, 0x10000U); /* todo: is necessary? */
1437
Marshall Dawson24f73d42019-04-01 10:48:43 -06001438 if (multi) {
1439 /* Do 2nd PSP directory followed by 1st */
1440 psp_directory_table *pspdir2 = new_psp_dir(&ctx, multi);
1441 integrate_psp_firmwares(&ctx, pspdir2, 0,
1442 amd_psp_fw_table, PSPL2_COOKIE);
1443
1444 pspdir = new_psp_dir(&ctx, multi);
1445 integrate_psp_firmwares(&ctx, pspdir, pspdir2,
1446 amd_psp_fw_table, PSP_COOKIE);
1447 } else {
1448 /* flat: PSP 1 cookie and no pointer to 2nd table */
1449 pspdir = new_psp_dir(&ctx, multi);
1450 integrate_psp_firmwares(&ctx, pspdir, 0,
1451 amd_psp_fw_table, PSP_COOKIE);
1452 }
Marshall Dawson2794a862019-03-04 16:53:15 -07001453
Marshall Dawson0e02ce82019-03-04 16:50:37 -07001454 if (comboable)
Marshall Dawson2794a862019-03-04 16:53:15 -07001455 amd_romsig->comboable = BUFF_TO_RUN(ctx, pspdir);
Marshall Dawson67d868d2019-02-28 11:43:40 -07001456 else
Marshall Dawson2794a862019-03-04 16:53:15 -07001457 amd_romsig->psp_entry = BUFF_TO_RUN(ctx, pspdir);
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001458
zbaoc3a08a92016-03-02 14:47:27 +08001459#if PSP_COMBO
Marshall Dawson2794a862019-03-04 16:53:15 -07001460 psp_combo_directory *combo_dir = new_combo_dir(&ctx);
1461 amd_romsig->comboable = BUFF_TO_RUN(ctx, combo_dir);
Marshall Dawson0e02ce82019-03-04 16:50:37 -07001462 /* 0 -Compare PSP ID, 1 -Compare chip family ID */
1463 combo_dir->entries[0].id_sel = 0;
1464 /* TODO: PSP ID. Documentation is needed. */
1465 combo_dir->entries[0].id = 0x10220B00;
Marshall Dawson2794a862019-03-04 16:53:15 -07001466 combo_dir->entries[0].lvl2_addr = BUFF_TO_RUN(ctx, pspdir);
Zheng Bao4fcc9f22015-11-20 12:29:04 +08001467
Marshall Dawson0e02ce82019-03-04 16:50:37 -07001468 combo_dir->header.lookup = 1;
Marshall Dawsona378c222019-03-04 16:52:07 -07001469 fill_dir_header(combo_dir, 1, PSP2_COOKIE);
Marshall Dawson0e02ce82019-03-04 16:50:37 -07001470#endif
Zheng Bao4fcc9f22015-11-20 12:29:04 +08001471
Marshall Dawsonce2b2ba2019-03-19 14:45:31 -06001472 if (have_bios_tables(amd_bios_table)) {
1473 bios_directory_table *biosdir;
1474 if (multi) {
1475 /* Do 2nd level BIOS directory followed by 1st */
1476 bios_directory_table *biosdir2 =
1477 new_bios_dir(&ctx, multi);
1478 integrate_bios_firmwares(&ctx, biosdir2, 0,
1479 amd_bios_table, BDT2_COOKIE);
1480
1481 biosdir = new_bios_dir(&ctx, multi);
1482 integrate_bios_firmwares(&ctx, biosdir, biosdir2,
1483 amd_bios_table, BDT1_COOKIE);
1484 } else {
1485 /* flat: BDT1 cookie and no pointer to 2nd table */
1486 biosdir = new_bios_dir(&ctx, multi);
1487 integrate_bios_firmwares(&ctx, biosdir, 0,
1488 amd_bios_table, BDT1_COOKIE);
1489 }
1490 amd_romsig->bios1_entry = BUFF_TO_RUN(ctx, biosdir);
1491 }
1492
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001493 targetfd = open(output, O_RDWR | O_CREAT | O_TRUNC, 0666);
Martin Roth31d95a22016-11-08 11:22:12 -07001494 if (targetfd >= 0) {
Marshall Dawson2794a862019-03-04 16:53:15 -07001495 write(targetfd, amd_romsig, ctx.current - romsig_offset);
Martin Roth31d95a22016-11-08 11:22:12 -07001496 close(targetfd);
1497 } else {
1498 printf("Error: could not open file: %s\n", output);
1499 retval = 1;
1500 }
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001501
Martin Roth31d95a22016-11-08 11:22:12 -07001502 free(rom);
1503 return retval;
Zheng Bao9c7ff7b2015-11-17 22:57:39 +08001504}