| Aaron Durbin | 1592169 | 2013-11-12 16:44:18 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <stdint.h> |
| 21 | #include <arch/io.h> |
| 22 | #include <console/console.h> |
| 23 | #include <device/device.h> |
| 24 | #include <device/pci.h> |
| 25 | #include <device/pci_ids.h> |
| 26 | #include <reg_script.h> |
| 27 | |
| 28 | #include <baytrail/iosf.h> |
| 29 | #include <baytrail/pci_devs.h> |
| 30 | #include <baytrail/ramstage.h> |
| 31 | |
| 32 | static const struct reg_script emmc_ops[] = { |
| 33 | /* Enable 2ms card stable feature. */ |
| 34 | REG_PCI_OR32(0xa8, (1 << 24)), |
| 35 | /* Enable HS200 */ |
| 36 | REG_PCI_WRITE32(0xa0, 0x446cc801), |
| 37 | REG_PCI_WRITE32(0xa4, 0x80000807), |
| 38 | /* cfio_regs_score_special_bits.sdio1_dummy_loopback_en=1 */ |
| 39 | REG_IOSF_OR(IOSF_PORT_SCORE, 0x49c0, (1 << 3)), |
| 40 | /* CLKGATE_EN_1 . cr_scc_mipihsi_clkgate_en = 1 */ |
| 41 | REG_IOSF_RMW(IOSF_PORT_CCU, 0x1c, ~(3 << 26), (1 << 26)), |
| 42 | /* Set slew for HS200 */ |
| 43 | REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c0, ~0x3c, 0x3c), |
| 44 | REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c4, ~0x3c, 0x3c), |
| 45 | /* Max timeout */ |
| 46 | REG_RES_WRITE8(PCI_BASE_ADDRESS_0, 0x002e, 0x0e), |
| 47 | REG_SCRIPT_END, |
| 48 | }; |
| 49 | |
| 50 | static void emmc_init(device_t dev) |
| 51 | { |
| 52 | struct reg_script ops[] = { |
| 53 | REG_SCRIPT_SET_DEV(dev), |
| 54 | REG_SCRIPT_NEXT(emmc_ops), |
| 55 | REG_SCRIPT_END, |
| 56 | }; |
| 57 | printk(BIOS_DEBUG, "eMMC init\n"); |
| 58 | reg_script_run(ops); |
| 59 | } |
| 60 | |
| 61 | static struct device_operations device_ops = { |
| 62 | .read_resources = pci_dev_read_resources, |
| 63 | .set_resources = pci_dev_set_resources, |
| 64 | .enable_resources = pci_dev_enable_resources, |
| 65 | .init = emmc_init, |
| 66 | .enable = NULL, |
| 67 | .scan_bus = NULL, |
| 68 | .ops_pci = &soc_pci_ops, |
| 69 | }; |
| 70 | |
| 71 | static const struct pci_driver southcluster __pci_driver = { |
| 72 | .ops = &device_ops, |
| 73 | .vendor = PCI_VENDOR_ID_INTEL, |
| 74 | .device = MMC_DEVID, |
| 75 | }; |