Angel Pons | e67ab18 | 2020-04-04 18:51:11 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Yidi Lin | 3d7b606 | 2015-07-31 17:10:40 +0800 | [diff] [blame] | 2 | |
| 3 | #include <memlayout.h> |
| 4 | |
| 5 | #include <arch/header.ld> |
| 6 | |
| 7 | /* |
| 8 | * SRAM_L2C is the half part of L2 cache that we borrow it to be used as SRAM. |
| 9 | * It will be returned before starting the ramstage. |
| 10 | * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able. |
| 11 | */ |
Julius Werner | 82d16b1 | 2020-12-30 15:51:10 -0800 | [diff] [blame] | 12 | #define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr) |
| 13 | #define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr) |
Yidi Lin | 3d7b606 | 2015-07-31 17:10:40 +0800 | [diff] [blame] | 14 | |
Yidi Lin | 0bdfec8 | 2016-02-16 20:42:10 +0800 | [diff] [blame] | 15 | #define DRAM_DMA(addr, size) \ |
| 16 | REGION(dram_dma, addr, size, 4K) \ |
| 17 | _ = ASSERT(size % 4K == 0, \ |
| 18 | "DRAM DMA buffer should be multiple of smallest page size (4K)!"); |
| 19 | |
Yidi Lin | 3d7b606 | 2015-07-31 17:10:40 +0800 | [diff] [blame] | 20 | SECTIONS |
| 21 | { |
| 22 | SRAM_L2C_START(0x000C0000) |
| 23 | BOOTBLOCK(0x000C1000, 85K) |
| 24 | VERSTAGE(0x000D7000, 114K) |
Yidi Lin | 3d7b606 | 2015-07-31 17:10:40 +0800 | [diff] [blame] | 25 | SRAM_L2C_END(0x00100000) |
| 26 | |
| 27 | SRAM_START(0x00100000) |
| 28 | VBOOT2_WORK(0x00100000, 12K) |
Sergii Dmytruk | 2710df7 | 2022-11-10 00:40:51 +0200 | [diff] [blame] | 29 | TPM_LOG(0x00103000, 2K) |
Julius Werner | cefe89e | 2019-11-06 19:29:44 -0800 | [diff] [blame] | 30 | FMAP_CACHE(0x00103800, 2K) |
| 31 | PRERAM_CBMEM_CONSOLE(0x00104000, 12K) |
Julius Werner | c713594 | 2016-03-23 16:08:11 -0700 | [diff] [blame] | 32 | WATCHDOG_TOMBSTONE(0x00107000, 4) |
Julius Werner | baf27db | 2019-10-02 17:28:56 -0700 | [diff] [blame] | 33 | PRERAM_CBFS_CACHE(0x00107004, 8K - 4) |
| 34 | CBFS_MCACHE(0x00109000, 8K) |
Yidi Lin | 5e2cfb5 | 2015-11-23 15:08:44 +0800 | [diff] [blame] | 35 | TIMESTAMP(0x0010B000, 4K) |
| 36 | ROMSTAGE(0x0010C000, 92K) |
Yidi Lin | 3d7b606 | 2015-07-31 17:10:40 +0800 | [diff] [blame] | 37 | STACK(0x00124000, 16K) |
| 38 | TTB(0x00128000, 28K) |
| 39 | DMA_COHERENT(0x0012F000, 4K) |
| 40 | SRAM_END(0x00130000) |
| 41 | |
| 42 | DRAM_START(0x40000000) |
Yidi Lin | 0bdfec8 | 2016-02-16 20:42:10 +0800 | [diff] [blame] | 43 | DRAM_DMA(0x40000000, 1M) |
Yidi Lin | 3d7b606 | 2015-07-31 17:10:40 +0800 | [diff] [blame] | 44 | POSTRAM_CBFS_CACHE(0x40100000, 1M) |
| 45 | RAMSTAGE(0x40200000, 256K) |
| 46 | } |