Patrick Georgi | be61a17 | 2010-12-18 07:48:43 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * Copyright (C) 2009-2010 iWave Systems |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 20 | */ |
| 21 | |
| 22 | #include <console/console.h> |
| 23 | #include <device/device.h> |
| 24 | #include <device/pci.h> |
| 25 | #include <device/pci_ids.h> |
| 26 | |
| 27 | static void pci_init(struct device *dev) |
| 28 | { |
| 29 | u16 reg16; |
| 30 | u32 reg32; |
| 31 | |
| 32 | printk(BIOS_DEBUG, "Initializing SCH PCIe bridge.\n"); |
| 33 | |
| 34 | /* Enable Bus Master */ |
| 35 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 36 | reg32 |= PCI_COMMAND_MASTER; |
| 37 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 38 | |
| 39 | /* Set Cache Line Size to 0x10 */ |
| 40 | // This has no effect but the OS might expect it |
| 41 | pci_write_config8(dev, 0x0c, 0x10); |
| 42 | //pci_write_config32(dev, 0x18, 0x11); |
| 43 | |
| 44 | //reg16 = pci_read_config16(dev, 0x3e); |
| 45 | //reg16 &= ~(1 << 0); /* disable parity error response */ |
| 46 | // reg16 &= ~(1 << 1); /* disable SERR */ |
| 47 | //reg16 |= (1 << 2); /* ISA enable */ |
| 48 | //pci_write_config16(dev, 0x3e, reg16); |
Uwe Hermann | 405721d | 2010-12-18 13:22:37 +0000 | [diff] [blame^] | 49 | /* Slot implemented. */ |
Patrick Georgi | be61a17 | 2010-12-18 07:48:43 +0000 | [diff] [blame] | 50 | reg16 = pci_read_config16(dev, 0x42); |
| 51 | reg16 |= (1 << 8); |
| 52 | pci_write_config16(dev, 0x42, reg16); |
| 53 | |
| 54 | reg16 = pci_read_config16(dev, 0x48); |
| 55 | reg16 |= 0xf; |
| 56 | pci_write_config16(dev, 0x48, reg16); |
Patrick Georgi | be61a17 | 2010-12-18 07:48:43 +0000 | [diff] [blame] | 57 | } |
| 58 | |
| 59 | static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 60 | { |
| 61 | /* NOTE: This is not the default position! */ |
| 62 | if (!vendor || !device) { |
Uwe Hermann | 405721d | 2010-12-18 13:22:37 +0000 | [diff] [blame^] | 63 | pci_write_config32(dev, 0x94, pci_read_config32(dev, 0)); |
Patrick Georgi | be61a17 | 2010-12-18 07:48:43 +0000 | [diff] [blame] | 64 | } else { |
| 65 | pci_write_config32(dev, 0x94, |
| 66 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 67 | } |
| 68 | } |
| 69 | |
| 70 | static struct pci_operations pci_ops = { |
| 71 | .set_subsystem = pcie_set_subsystem, |
| 72 | }; |
| 73 | |
| 74 | static struct device_operations device_ops = { |
| 75 | .read_resources = pci_bus_read_resources, |
| 76 | .set_resources = pci_dev_set_resources, |
| 77 | .enable_resources = pci_bus_enable_resources, |
| 78 | .init = pci_init, |
| 79 | .scan_bus = pci_scan_bridge, |
| 80 | .ops_pci = &pci_ops, |
| 81 | }; |
| 82 | |
| 83 | /* Port 1 */ |
| 84 | static const struct pci_driver sch_pcie_port1 __pci_driver = { |
| 85 | .ops = &device_ops, |
| 86 | .vendor = PCI_VENDOR_ID_INTEL, |
| 87 | .device = 0x8110, |
| 88 | }; |
| 89 | |
| 90 | /*Port 2 */ |
| 91 | static const struct pci_driver sch_pcie_port2 __pci_driver = { |
| 92 | .ops = &device_ops, |
| 93 | .vendor = PCI_VENDOR_ID_INTEL, |
| 94 | .device = 0x8112, |
| 95 | }; |