blob: 4c71f285ebcb520fe60b5cea7e6212136d8ee7bd [file] [log] [blame]
Patrick Georgi0588d192009-08-12 15:00:51 +00001##
Stefan Reinauer16f515a2010-01-20 18:44:30 +00002## This file is part of the coreboot project.
Patrick Georgi0588d192009-08-12 15:00:51 +00003##
Alexandru Gagniuc70c660f2012-08-23 02:32:58 -05004## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
Stefan Reinauer16f515a2010-01-20 18:44:30 +00005## Copyright (C) 2009-2010 coresystems GmbH
Patrick Georgi0588d192009-08-12 15:00:51 +00006##
Stefan Reinauer16f515a2010-01-20 18:44:30 +00007## This program is free software; you can redistribute it and/or modify
8## it under the terms of the GNU General Public License as published by
9## the Free Software Foundation; version 2 of the License.
10##
11## This program is distributed in the hope that it will be useful,
12## but WITHOUT ANY WARRANTY; without even the implied warranty of
13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14## GNU General Public License for more details.
15##
Patrick Georgi0588d192009-08-12 15:00:51 +000016
Uwe Hermannad8c95f2012-04-12 22:00:03 +020017mainmenu "coreboot configuration"
Patrick Georgi0588d192009-08-12 15:00:51 +000018
Uwe Hermannc04be932009-10-05 13:55:28 +000019menu "General setup"
20
Lee Leahybb70c402017-04-03 07:38:20 -070021config COREBOOT_BUILD
22 bool
23 default y
24
Uwe Hermannc04be932009-10-05 13:55:28 +000025config LOCALVERSION
Uwe Hermann168b11b2009-10-07 16:15:40 +000026 string "Local version string"
Uwe Hermannc04be932009-10-05 13:55:28 +000027 help
28 Append an extra string to the end of the coreboot version.
29
Uwe Hermann168b11b2009-10-07 16:15:40 +000030 This can be useful if, for instance, you want to append the
31 respective board's hostname or some other identifying string to
32 the coreboot version number, so that you can easily distinguish
33 boot logs of different boards from each other.
34
Arthur Heymans6f751542019-06-08 11:28:52 +020035config CONFIGURABLE_CBFS_PREFIX
36 bool
37 help
38 Select this to prompt to use to configure the prefix for cbfs files.
39
Arthur Heymans6010eb22019-10-06 13:34:20 +020040choice
41 prompt "CBFS prefix to use"
42 depends on CONFIGURABLE_CBFS_PREFIX
43 default CBFS_PREFIX_FALLBACK
44
45config CBFS_PREFIX_FALLBACK
46 bool "fallback"
47
48config CBFS_PREFIX_NORMAL
49 bool "normal"
50
51config CBFS_PREFIX_DIY
52 bool "Define your own cbfs prefix"
53
54endchoice
55
Patrick Georgi4b8a2412010-02-09 19:35:16 +000056config CBFS_PREFIX
Arthur Heymans6010eb22019-10-06 13:34:20 +020057 string "CBFS prefix to use" if CBFS_PREFIX_DIY
58 default "fallback" if !CONFIGURABLE_CBFS_PREFIX || CBFS_PREFIX_FALLBACK
59 default "normal" if CBFS_PREFIX_NORMAL
Patrick Georgi4b8a2412010-02-09 19:35:16 +000060 help
61 Select the prefix to all files put into the image. It's "fallback"
62 by default, "normal" is a common alternative.
63
Patrick Georgi23d89cc2010-03-16 01:17:19 +000064choice
Uwe Hermannad8c95f2012-04-12 22:00:03 +020065 prompt "Compiler to use"
Patrick Georgi23d89cc2010-03-16 01:17:19 +000066 default COMPILER_GCC
67 help
68 This option allows you to select the compiler used for building
69 coreboot.
Martin Rotha5a628e82016-01-19 12:01:09 -070070 You must build the coreboot crosscompiler for the board that you
71 have selected.
72
73 To build all the GCC crosscompilers (takes a LONG time), run:
74 make crossgcc
75
76 For help on individual architectures, run the command:
77 make help_toolchain
Patrick Georgi23d89cc2010-03-16 01:17:19 +000078
79config COMPILER_GCC
80 bool "GCC"
Uwe Hermannad8c95f2012-04-12 22:00:03 +020081 help
82 Use the GNU Compiler Collection (GCC) to build coreboot.
83
84 For details see http://gcc.gnu.org.
85
Patrick Georgi23d89cc2010-03-16 01:17:19 +000086config COMPILER_LLVM_CLANG
Martin Rotha5a628e82016-01-19 12:01:09 -070087 bool "LLVM/clang (TESTING ONLY - Not currently working)"
Uwe Hermannad8c95f2012-04-12 22:00:03 +020088 help
Martin Rotha5a628e82016-01-19 12:01:09 -070089 Use LLVM/clang to build coreboot. To use this, you must build the
90 coreboot version of the clang compiler. Run the command
91 make clang
92 Note that this option is not currently working correctly and should
93 really only be selected if you're trying to work on getting clang
94 operational.
Uwe Hermannad8c95f2012-04-12 22:00:03 +020095
96 For details see http://clang.llvm.org.
97
Patrick Georgi23d89cc2010-03-16 01:17:19 +000098endchoice
99
Patrick Georgi9b0de712013-12-29 18:45:23 +0100100config ANY_TOOLCHAIN
101 bool "Allow building with any toolchain"
102 default n
Patrick Georgi9b0de712013-12-29 18:45:23 +0100103 help
104 Many toolchains break when building coreboot since it uses quite
105 unusual linker features. Unless developers explicitely request it,
106 we'll have to assume that they use their distro compiler by mistake.
107 Make sure that using patched compilers is a conscious decision.
108
Patrick Georgi516a2a72010-03-25 21:45:25 +0000109config CCACHE
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200110 bool "Use ccache to speed up (re)compilation"
Patrick Georgi516a2a72010-03-25 21:45:25 +0000111 default n
112 help
113 Enables the use of ccache for faster builds.
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200114
115 Requires the ccache utility in your system $PATH.
116
117 For details see https://ccache.samba.org.
Patrick Georgi516a2a72010-03-25 21:45:25 +0000118
Sol Boucher69b88bf2015-02-26 11:47:19 -0800119config FMD_GENPARSER
120 bool "Generate flashmap descriptor parser using flex and bison"
121 default n
Sol Boucher69b88bf2015-02-26 11:47:19 -0800122 help
123 Enable this option if you are working on the flashmap descriptor
124 parser and made changes to fmd_scanner.l or fmd_parser.y.
125
126 Otherwise, say N to use the provided pregenerated scanner/parser.
127
Martin Rothf411b702017-04-09 19:12:42 -0600128config UTIL_GENPARSER
Denis 'GNUtoo' Carikli780e9312018-01-10 14:35:55 +0100129 bool "Generate SCONFIG & BINCFG parser using flex and bison"
Stefan Reinauer9bf78102010-08-09 13:28:18 +0000130 default n
Stefan Reinauer9bf78102010-08-09 13:28:18 +0000131 help
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200132 Enable this option if you are working on the sconfig device tree
Denis 'GNUtoo' Carikli780e9312018-01-10 14:35:55 +0100133 parser or bincfg and made changes to the .l or .y files.
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200134
Sol Boucher69b88bf2015-02-26 11:47:19 -0800135 Otherwise, say N to use the provided pregenerated scanner/parser.
Stefan Reinauer9bf78102010-08-09 13:28:18 +0000136
Joe Korty6d772522010-05-19 18:41:15 +0000137config USE_OPTION_TABLE
138 bool "Use CMOS for configuration values"
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000139 depends on HAVE_OPTION_TABLE
Joe Korty6d772522010-05-19 18:41:15 +0000140 help
141 Enable this option if coreboot shall read options from the "CMOS"
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200142 NVRAM instead of using hard-coded values.
Joe Korty6d772522010-05-19 18:41:15 +0000143
Timothy Pearsonf20c6e82015-02-14 16:15:31 -0600144config STATIC_OPTION_TABLE
145 bool "Load default configuration values into CMOS on each boot"
Timothy Pearsonf20c6e82015-02-14 16:15:31 -0600146 depends on USE_OPTION_TABLE
147 help
148 Enable this option to reset "CMOS" NVRAM values to default on
149 every boot. Use this if you want the NVRAM configuration to
150 never be modified from its default values.
151
Sven Schnelle8eee19d2011-05-02 19:53:04 +0000152config COMPRESS_RAMSTAGE
153 bool "Compress ramstage with LZMA"
Subrata Banikb5962a92019-06-08 12:29:02 +0530154 depends on HAVE_RAMSTAGE
Martin Roth75e5cb72016-12-15 15:05:37 -0700155 # Default value set at the end of the file
Sven Schnelle8eee19d2011-05-02 19:53:04 +0000156 help
157 Compress ramstage to save memory in the flash image. Note
158 that decompression might slow down booting if the boot flash
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200159 is connected through a slow link (i.e. SPI).
Sven Schnelle8eee19d2011-05-02 19:53:04 +0000160
Julius Werner09f29212015-09-29 13:51:35 -0700161config COMPRESS_PRERAM_STAGES
162 bool "Compress romstage and verstage with LZ4"
Subrata Banikb5962a92019-06-08 12:29:02 +0530163 depends on !ARCH_X86 && (HAVE_ROMSTAGE || HAVE_VERSTAGE)
Martin Roth75e5cb72016-12-15 15:05:37 -0700164 # Default value set at the end of the file
Julius Werner09f29212015-09-29 13:51:35 -0700165 help
166 Compress romstage and (if it exists) verstage with LZ4 to save flash
167 space and speed up boot, since the time for reading the image from SPI
168 (and in the vboot case verifying it) is usually much greater than the
169 time spent decompressing. Doesn't work for XIP stages (assume all
170 ARCH_X86 for now) for obvious reasons.
171
Julius Werner99f46832018-05-16 14:14:04 -0700172config COMPRESS_BOOTBLOCK
173 bool
Subrata Banikb5962a92019-06-08 12:29:02 +0530174 depends on HAVE_BOOTBLOCK
Julius Werner99f46832018-05-16 14:14:04 -0700175 help
176 This option can be used to compress the bootblock with LZ4 and attach
177 a small self-decompression stub to its front. This can drastically
178 reduce boot time on platforms where the bootblock is loaded over a
179 very slow connection and bootblock size trumps all other factors for
Jonathan Neuschäfer2930a722018-09-29 17:42:52 +0200180 speed. Since using this option usually requires changes to the
Julius Werner99f46832018-05-16 14:14:04 -0700181 SoC memlayout and possibly extra support code, it should not be
182 user-selectable. (There's no real point in offering this to the user
183 anyway... if it works and saves boot time, you would always want it.)
184
Cristian Măgherușan-Stanciud367b002011-06-19 03:03:28 +0200185config INCLUDE_CONFIG_FILE
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200186 bool "Include the coreboot .config file into the ROM image"
Martin Roth75e5cb72016-12-15 15:05:37 -0700187 # Default value set at the end of the file
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200188 help
189 Include the .config file that was used to compile coreboot
190 in the (CBFS) ROM image. This is useful if you want to know which
191 options were used to build a specific coreboot.rom image.
192
Daniele Forsi53847a22014-07-22 18:00:56 +0200193 Saying Y here will increase the image size by 2-3KB.
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200194
195 You can use the following command to easily list the options:
196
197 grep -a CONFIG_ coreboot.rom
198
199 Alternatively, you can also use cbfstool to print the image
200 contents (including the raw 'config' item we're looking for).
201
202 Example:
203
204 $ cbfstool coreboot.rom print
205 coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
206 offset 0x0
207 Alignment: 64 bytes
Steve Goodrichf0269122012-05-18 11:18:47 -0600208
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200209 Name Offset Type Size
210 cmos_layout.bin 0x0 cmos layout 1159
211 fallback/romstage 0x4c0 stage 339756
Daniele Forsi53847a22014-07-22 18:00:56 +0200212 fallback/ramstage 0x53440 stage 186664
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200213 fallback/payload 0x80dc0 payload 51526
214 config 0x8d740 raw 3324
215 (empty) 0x8e480 null 3610440
Cristian Măgherușan-Stanciud367b002011-06-19 03:03:28 +0200216
Vadim Bendebury9202473d2011-09-21 14:46:43 -0700217config COLLECT_TIMESTAMPS
218 bool "Create a table of timestamps collected during boot"
Paul Menzel4e4a7632015-10-11 11:57:44 +0200219 default y if ARCH_X86
Vadim Bendebury9202473d2011-09-21 14:46:43 -0700220 help
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200221 Make coreboot create a table of timer-ID/timer-value pairs to
222 allow measuring time spent at different phases of the boot process.
223
Martin Rothb22bbe22018-03-07 15:32:16 -0700224config TIMESTAMPS_ON_CONSOLE
225 bool "Print the timestamp values on the console"
226 default n
227 depends on COLLECT_TIMESTAMPS
228 help
229 Print the timestamps to the debug console if enabled at level spew.
230
Patrick Georgi7e9b9d82012-04-30 21:06:10 +0200231config USE_BLOBS
232 bool "Allow use of binary-only repository"
Patrick Georgi7e9b9d82012-04-30 21:06:10 +0200233 help
234 This draws in the blobs repository, which contains binary files that
235 might be required for some chipsets or boards.
236 This flag ensures that a "Free" option remains available for users.
237
Stefan Reinauerd37ab452012-12-18 16:23:28 -0800238config COVERAGE
239 bool "Code coverage support"
240 depends on COMPILER_GCC
Stefan Reinauerd37ab452012-12-18 16:23:28 -0800241 help
242 Add code coverage support for coreboot. This will store code
243 coverage information in CBMEM for extraction from user space.
244 If unsure, say N.
245
Ryan Salsamendiab37e9a2017-06-11 21:07:31 -0700246config UBSAN
247 bool "Undefined behavior sanitizer support"
248 default n
249 help
250 Instrument the code with checks for undefined behavior. If unsure,
251 say N because it adds a small performance penalty and may abort
252 on code that happens to work in spite of the UB.
253
Kyösti Mälkki7904e722018-06-03 14:55:10 +0300254config NO_RELOCATABLE_RAMSTAGE
255 bool
256 default n if ARCH_X86
257 default y
258
Stefan Reinauer58470e32014-10-17 13:08:36 +0200259config RELOCATABLE_RAMSTAGE
Kyösti Mälkki730df3c2016-06-18 07:39:31 +0300260 bool
Kyösti Mälkki730df3c2016-06-18 07:39:31 +0300261 default !NO_RELOCATABLE_RAMSTAGE
Vladimir Serbinenko633352c2015-05-30 22:21:37 +0200262 select RELOCATABLE_MODULES
Stefan Reinauer58470e32014-10-17 13:08:36 +0200263 help
264 The reloctable ramstage support allows for the ramstage to be built
265 as a relocatable module. The stage loader can identify a place
266 out of the OS way so that copying memory is unnecessary during an S3
267 wake. When selecting this option the romstage is responsible for
268 determing a stack location to use for loading the ramstage.
269
Kyösti Mälkki0a4457f2019-08-01 20:29:14 +0300270config TSEG_STAGE_CACHE
Arthur Heymans410f2562017-01-25 15:27:52 +0100271 bool
Kyösti Mälkki0a4457f2019-08-01 20:29:14 +0300272 default y
273 depends on !NO_STAGE_CACHE && SMM_TSEG
Stefan Reinauer58470e32014-10-17 13:08:36 +0200274 help
Kyösti Mälkki0a4457f2019-08-01 20:29:14 +0300275 The option enables stage cache support for platform. Platform
276 can stash copies of postcar, ramstage and raw runtime data
277 inside SMM TSEG, to be restored on S3 resume path.
278
279config CBMEM_STAGE_CACHE
280 bool "Cache stages in CBMEM"
281 depends on !NO_STAGE_CACHE && !TSEG_STAGE_CACHE
282 help
283 The option enables stage cache support for platform. Platform
284 can stash copies of postcar, ramstage and raw runtime data
285 inside CBMEM.
286
287 While the approach is faster than reloading stages from boot media
288 it is also a possible attack scenario via which OS can possibly
289 circumvent SMM locks and SPI write protections.
290
291 If unsure, select 'N'
Stefan Reinauer58470e32014-10-17 13:08:36 +0200292
Stefan Reinauer58470e32014-10-17 13:08:36 +0200293config UPDATE_IMAGE
294 bool "Update existing coreboot.rom image"
Stefan Reinauer58470e32014-10-17 13:08:36 +0200295 help
296 If this option is enabled, no new coreboot.rom file
297 is created. Instead it is expected that there already
298 is a suitable file for further processing.
299 The bootblock will not be modified.
300
Martin Roth5942e062016-01-20 14:59:21 -0700301 If unsure, select 'N'
302
Konstantin Aladyshev6544cb32015-01-24 18:52:10 +0400303config BOOTSPLASH_IMAGE
304 bool "Add a bootsplash image"
305 help
306 Select this option if you have a bootsplash image that you would
307 like to add to your ROM.
308
309 This will only add the image to the ROM. To actually run it check
310 options under 'Display' section.
311
312config BOOTSPLASH_FILE
313 string "Bootsplash path and filename"
314 depends on BOOTSPLASH_IMAGE
Martin Roth75e5cb72016-12-15 15:05:37 -0700315 # Default value set at the end of the file
Konstantin Aladyshev6544cb32015-01-24 18:52:10 +0400316 help
317 The path and filename of the file to use as graphical bootsplash
318 screen. The file format has to be jpg.
319
Nico Huber94cdec62019-06-06 19:36:02 +0200320config HAVE_RAMPAYLOAD
321 bool
322
Subrata Banik7e893a02019-05-06 14:17:41 +0530323config RAMPAYLOAD
324 bool "Enable coreboot flow without executing ramstage"
Subrata Banik86dbe0f2019-06-28 18:18:37 +0530325 default y if ARCH_X86
Nico Huber94cdec62019-06-06 19:36:02 +0200326 depends on HAVE_RAMPAYLOAD
Subrata Banik7e893a02019-05-06 14:17:41 +0530327 help
328 If this option is enabled, coreboot flow will skip ramstage
329 loading and execution of ramstage to load payload.
330
331 Instead it is expected to load payload from postcar stage itself.
332
333 In this flow coreboot will perform basic x86 initialization
334 (DRAM resource allocation), MTRR programming,
335 Skip PCI enumeration logic and only allocate BAR for fixed devices
336 (bootable devices, TPM over GSPI).
337
Uwe Hermannc04be932009-10-05 13:55:28 +0000338endmenu
339
Martin Roth026e4dc2015-06-19 23:17:15 -0600340menu "Mainboard"
341
Stefan Reinauera48ca842015-04-04 01:58:28 +0200342source "src/mainboard/Kconfig"
Stefan Reinauer8aedcbc2010-12-16 23:37:17 +0000343
Marshall Dawsone9375132016-09-04 08:38:33 -0600344config DEVICETREE
345 string
346 default "devicetree.cb"
347 help
348 This symbol allows mainboards to select a different file under their
349 mainboard directory for the devicetree.cb file. This allows the board
350 variants that need different devicetrees to be in the same directory.
351
352 Examples: "devicetree.variant.cb"
353 "variant/devicetree.cb"
354
Furquan Shaikhf2419982018-06-21 18:50:48 -0700355config OVERRIDE_DEVICETREE
356 string
357 default ""
358 help
359 This symbol allows variants to provide an override devicetree file to
360 override the registers and/or add new devices on top of the ones
361 provided by baseboard devicetree using CONFIG_DEVICETREE.
362
363 Examples: "devicetree.variant-override.cb"
364 "variant/devicetree-override.cb"
365
Patrick Georgi8a3592e2015-09-16 18:10:52 +0200366config FMDFILE
367 string "fmap description file in fmd format"
Patrick Georgi5d7ab392015-12-12 00:23:15 +0100368 default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
Patrick Georgi8a3592e2015-09-16 18:10:52 +0200369 default ""
370 help
371 The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
372 but in some cases more complex setups are required.
373 When an fmd is specified, it overrides the default format.
374
Arthur Heymans965881b2019-09-25 13:18:52 +0200375config CBFS_SIZE
376 hex "Size of CBFS filesystem in ROM"
377 depends on FMDFILE = ""
378 # Default value set at the end of the file
379 help
380 This is the part of the ROM actually managed by CBFS, located at the
381 end of the ROM (passed through cbfstool -o) on x86 and at at the start
382 of the ROM (passed through cbfstool -s) everywhere else. It defaults
383 to span the whole ROM on all but Intel systems that use an Intel Firmware
384 Descriptor. It can be overridden to make coreboot live alongside other
385 components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
386 binaries. This symbol should only be used to generate a default FMAP and
387 is unused when a non-default fmd file is provided via CONFIG_FMDFILE.
388
Martin Rothda1ca202015-12-26 16:51:16 -0700389endmenu
390
Martin Rothb09a5692016-01-24 19:38:33 -0700391# load site-local kconfig to allow user specific defaults and overrides
392source "site-local/Kconfig"
393
Vladimir Serbinenkoa9db82f2014-10-16 13:21:47 +0200394config SYSTEM_TYPE_LAPTOP
Martin Roth595e7772015-04-26 18:53:26 -0600395 default n
396 bool
Vladimir Serbinenkoa9db82f2014-10-16 13:21:47 +0200397
Duncan Laurie8312df42019-02-01 11:33:57 -0800398config SYSTEM_TYPE_TABLET
399 default n
400 bool
401
402config SYSTEM_TYPE_DETACHABLE
403 default n
404 bool
405
406config SYSTEM_TYPE_CONVERTIBLE
407 default n
408 bool
409
Werner Zehc0fb3612016-01-14 15:08:36 +0100410config CBFS_AUTOGEN_ATTRIBUTES
411 default n
412 bool
413 help
414 If this option is selected, every file in cbfs which has a constraint
415 regarding position or alignment will get an additional file attribute
416 which describes this constraint.
417
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000418menu "Chipset"
419
Duncan Lauried2119762015-06-08 18:11:56 -0700420comment "SoC"
Chris Chingaa8e5d32017-10-20 10:43:39 -0600421source "src/soc/*/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000422comment "CPU"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200423source "src/cpu/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000424comment "Northbridge"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200425source "src/northbridge/*/*/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000426comment "Southbridge"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200427source "src/southbridge/*/*/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000428comment "Super I/O"
Omar Pakker57603e22016-07-29 23:31:45 +0200429source "src/superio/*/*/Kconfig"
Sven Schnelle7592e8b2011-01-27 11:43:03 +0000430comment "Embedded Controllers"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200431source "src/ec/acpi/Kconfig"
432source "src/ec/*/*/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000433
Martin Roth59aa2b12015-06-20 16:17:12 -0600434source "src/southbridge/intel/common/firmware/Kconfig"
Martin Rothe1523ec2015-06-19 22:30:43 -0600435source "src/vendorcode/*/Kconfig"
Martin Roth59aa2b12015-06-20 16:17:12 -0600436
Martin Rothe1523ec2015-06-19 22:30:43 -0600437source "src/arch/*/Kconfig"
438
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000439endmenu
Patrick Georgi0588d192009-08-12 15:00:51 +0000440
Stefan Reinauera48ca842015-04-04 01:58:28 +0200441source "src/device/Kconfig"
Stefan Reinauer95a63962012-11-13 17:00:01 -0800442
Rudolf Marekd9c25492010-05-16 15:31:53 +0000443menu "Generic Drivers"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200444source "src/drivers/*/Kconfig"
Stefan Reinauer86ddd732016-03-11 20:22:28 -0800445source "src/drivers/*/*/Kconfig"
Lee Leahy48dbc662017-05-08 16:56:03 -0700446source "src/commonlib/storage/Kconfig"
Rudolf Marekd9c25492010-05-16 15:31:53 +0000447endmenu
448
Philipp Deppenwiese1899fbe2017-10-16 17:09:33 +0200449menu "Security"
450
451source "src/security/Kconfig"
452
453endmenu
454
Martin Roth09210a12016-05-17 11:28:23 -0600455source "src/acpi/Kconfig"
456
Aaron Durbin4a36c4e2016-08-11 11:02:26 -0500457# This option is for the current boards/chipsets where SPI flash
458# is not the boot device. Currently nearly all boards/chipsets assume
459# SPI flash is the boot device.
460config BOOT_DEVICE_NOT_SPI_FLASH
461 bool
462 default n
463
464config BOOT_DEVICE_SPI_FLASH
465 bool
466 default y if !BOOT_DEVICE_NOT_SPI_FLASH
467 default n
468
Aaron Durbin16c173f2016-08-11 14:04:10 -0500469config BOOT_DEVICE_MEMORY_MAPPED
470 bool
471 default y if ARCH_X86 && BOOT_DEVICE_SPI_FLASH
472 default n
473 help
474 Inform system if SPI is memory-mapped or not.
475
Aaron Durbine8e118d2016-08-12 15:00:10 -0500476config BOOT_DEVICE_SUPPORTS_WRITES
477 bool
478 default n
479 help
480 Indicate that the platform has writable boot device
481 support.
482
Patrick Georgi0770f252015-04-22 13:28:21 +0200483config RTC
484 bool
485 default n
486
Patrick Georgi0588d192009-08-12 15:00:51 +0000487config HEAP_SIZE
488 hex
Marty E. Plummer0987e432019-04-22 20:46:27 -0500489 default 0x100000 if FLATTENED_DEVICE_TREE
Myles Watson04000f42009-10-16 19:12:49 +0000490 default 0x4000
Patrick Georgi0588d192009-08-12 15:00:51 +0000491
Julius Wernerc3e7c4e2014-09-19 13:18:16 -0700492config STACK_SIZE
493 hex
Julius Werner66a476a2015-10-12 16:45:21 -0700494 default 0x1000 if ARCH_X86
495 default 0x0
Julius Wernerc3e7c4e2014-09-19 13:18:16 -0700496
Patrick Georgi0588d192009-08-12 15:00:51 +0000497config MAX_CPUS
498 int
499 default 1
500
Stefan Reinauera48ca842015-04-04 01:58:28 +0200501source "src/console/Kconfig"
Patrick Georgi0588d192009-08-12 15:00:51 +0000502
503config HAVE_ACPI_RESUME
504 bool
505 default n
Kyösti Mälkki7cd2c072018-06-03 23:04:28 +0300506 depends on RELOCATABLE_RAMSTAGE
Patrick Georgi0588d192009-08-12 15:00:51 +0000507
Aaron Durbin87c9fae2016-01-22 15:26:04 -0600508config RESUME_PATH_SAME_AS_BOOT
509 bool
510 default y if ARCH_X86
511 depends on HAVE_ACPI_RESUME
512 help
513 This option indicates that when a system resumes it takes the
514 same path as a regular boot. e.g. an x86 system runs from the
515 reset vector at 0xfffffff0 on both resume and warm/cold boot.
516
Timothy Pearson44d53422015-05-18 16:04:10 -0500517config HAVE_ROMSTAGE_CONSOLE_SPINLOCK
518 bool
519 default n
520
Timothy Pearson7b22d842015-08-28 19:52:05 -0500521config HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK
522 bool
523 default n
524 help
525 This should be enabled on certain plaforms, such as the AMD
526 SR565x, that cannot handle concurrent CBFS accesses from
527 multiple APs during early startup.
528
Timothy Pearsonc764c742015-08-28 20:48:17 -0500529config HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK
530 bool
531 default n
532
Kyösti Mälkki76c43862019-07-01 17:25:41 +0300533config NO_MONOTONIC_TIMER
Aaron Durbina4217912013-04-29 22:31:51 -0500534 def_bool n
Kyösti Mälkki76c43862019-07-01 17:25:41 +0300535
536config HAVE_MONOTONIC_TIMER
537 bool
538 depends on !NO_MONOTONIC_TIMER
Kyösti Mälkkib28b6b52019-07-01 15:38:25 +0300539 default y
Aaron Durbina4217912013-04-29 22:31:51 -0500540 help
541 The board/chipset provides a monotonic timer.
542
Aaron Durbine5e36302014-09-25 10:05:15 -0500543config GENERIC_UDELAY
Kyösti Mälkki76c43862019-07-01 17:25:41 +0300544 bool
Aaron Durbine5e36302014-09-25 10:05:15 -0500545 depends on HAVE_MONOTONIC_TIMER
Kyösti Mälkki76c43862019-07-01 17:25:41 +0300546 default y if !ARCH_X86
Aaron Durbine5e36302014-09-25 10:05:15 -0500547 help
548 The board/chipset uses a generic udelay function utilizing the
549 monotonic timer.
550
Aaron Durbin340ca912013-04-30 09:58:12 -0500551config TIMER_QUEUE
552 def_bool n
553 depends on HAVE_MONOTONIC_TIMER
554 help
Kyösti Mälkkiecd84242013-09-13 07:57:49 +0300555 Provide a timer queue for performing time-based callbacks.
Aaron Durbin340ca912013-04-30 09:58:12 -0500556
Aaron Durbin4409a5e2013-05-06 12:20:52 -0500557config COOP_MULTITASKING
558 def_bool n
Aaron Durbin38c326d2013-05-06 12:22:23 -0500559 depends on TIMER_QUEUE && ARCH_X86
Aaron Durbin4409a5e2013-05-06 12:20:52 -0500560 help
561 Cooperative multitasking allows callbacks to be multiplexed on the
562 main thread of ramstage. With this enabled it allows for multiple
563 execution paths to take place when they have udelay() calls within
564 their code.
565
566config NUM_THREADS
567 int
568 default 4
569 depends on COOP_MULTITASKING
570 help
571 How many execution threads to cooperatively multitask with.
572
Patrick Georgi0588d192009-08-12 15:00:51 +0000573config HAVE_OPTION_TABLE
574 bool
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000575 default n
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000576 help
577 This variable specifies whether a given board has a cmos.layout
578 file containing NVRAM/CMOS bit definitions.
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000579 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
Patrick Georgi0588d192009-08-12 15:00:51 +0000580
Patrick Georgi0588d192009-08-12 15:00:51 +0000581config PCI_IO_CFG_EXT
582 bool
583 default n
584
585config IOAPIC
586 bool
587 default n
588
Myles Watson45bb25f2009-09-22 18:49:08 +0000589config USE_WATCHDOG_ON_BOOT
590 bool
591 default n
592
Myles Watson45bb25f2009-09-22 18:49:08 +0000593config GFXUMA
594 bool
Myles Watsond73c1b52009-10-26 15:14:07 +0000595 default n
Myles Watson45bb25f2009-09-22 18:49:08 +0000596 help
597 Enable Unified Memory Architecture for graphics.
598
Myles Watsonb8e20272009-10-15 13:35:47 +0000599config HAVE_ACPI_TABLES
600 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000601 help
602 This variable specifies whether a given board has ACPI table support.
603 It is usually set in mainboard/*/Kconfig.
Myles Watsonb8e20272009-10-15 13:35:47 +0000604
605config HAVE_MP_TABLE
606 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000607 help
608 This variable specifies whether a given board has MP table support.
609 It is usually set in mainboard/*/Kconfig.
610 Whether or not the MP table is actually generated by coreboot
611 is configurable by the user via GENERATE_MP_TABLE.
Myles Watsonb8e20272009-10-15 13:35:47 +0000612
613config HAVE_PIRQ_TABLE
614 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000615 help
616 This variable specifies whether a given board has PIRQ table support.
617 It is usually set in mainboard/*/Kconfig.
618 Whether or not the PIRQ table is actually generated by coreboot
619 is configurable by the user via GENERATE_PIRQ_TABLE.
Myles Watsonb8e20272009-10-15 13:35:47 +0000620
Vladimir Serbinenkoc21e0732014-10-16 12:48:19 +0200621config COMMON_FADT
622 bool
623 default n
624
Aaron Durbin9420a522015-11-17 16:31:00 -0600625config ACPI_NHLT
626 bool
627 default n
628 help
629 Build support for NHLT (non HD Audio) ACPI table generation.
630
Marshall Dawson991467d2018-09-04 12:32:56 -0600631config ACPI_BERT
632 bool
633 depends on HAVE_ACPI_TABLES
634 help
635 Build an ACPI Boot Error Record Table.
636
Myles Watsond73c1b52009-10-26 15:14:07 +0000637#These Options are here to avoid "undefined" warnings.
638#The actual selection and help texts are in the following menu.
639
Uwe Hermann168b11b2009-10-07 16:15:40 +0000640menu "System tables"
Myles Watson45bb25f2009-09-22 18:49:08 +0000641
Myles Watsonb8e20272009-10-15 13:35:47 +0000642config GENERATE_MP_TABLE
Stefan Reinauer56cd70b2012-11-13 17:33:08 -0800643 prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
644 bool
645 default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000646 help
647 Generate an MP table (conforming to the Intel MultiProcessor
648 specification 1.4) for this board.
649
650 If unsure, say Y.
Myles Watson45bb25f2009-09-22 18:49:08 +0000651
Myles Watsonb8e20272009-10-15 13:35:47 +0000652config GENERATE_PIRQ_TABLE
Stefan Reinauer56cd70b2012-11-13 17:33:08 -0800653 prompt "Generate a PIRQ table" if HAVE_PIRQ_TABLE
654 bool
655 default HAVE_PIRQ_TABLE
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000656 help
657 Generate a PIRQ table for this board.
658
659 If unsure, say Y.
Myles Watson45bb25f2009-09-22 18:49:08 +0000660
Sven Schnelle164bcfd2011-08-14 20:56:34 +0200661config GENERATE_SMBIOS_TABLES
662 depends on ARCH_X86
663 bool "Generate SMBIOS tables"
664 default y
665 help
666 Generate SMBIOS tables for this board.
667
668 If unsure, say Y.
669
Vladimir Serbinenko0afdec42015-05-30 23:08:26 +0200670config SMBIOS_PROVIDED_BY_MOBO
671 bool
672 default n
673
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200674config MAINBOARD_SERIAL_NUMBER
Nico Huberebd8a4f2017-11-01 09:49:16 +0100675 prompt "SMBIOS Serial Number" if !SMBIOS_PROVIDED_BY_MOBO
676 string
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200677 depends on GENERATE_SMBIOS_TABLES
678 default "123456789"
Martin Roth595e7772015-04-26 18:53:26 -0600679 help
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200680 The Serial Number to store in SMBIOS structures.
681
682config MAINBOARD_VERSION
Nico Huberebd8a4f2017-11-01 09:49:16 +0100683 prompt "SMBIOS Version Number" if !SMBIOS_PROVIDED_BY_MOBO
684 string
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200685 depends on GENERATE_SMBIOS_TABLES
686 default "1.0"
687 help
688 The Version Number to store in SMBIOS structures.
689
690config MAINBOARD_SMBIOS_MANUFACTURER
Nico Huberebd8a4f2017-11-01 09:49:16 +0100691 prompt "SMBIOS Manufacturer" if !SMBIOS_PROVIDED_BY_MOBO
692 string
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200693 depends on GENERATE_SMBIOS_TABLES
694 default MAINBOARD_VENDOR
695 help
696 Override the default Manufacturer stored in SMBIOS structures.
697
698config MAINBOARD_SMBIOS_PRODUCT_NAME
Nico Huberebd8a4f2017-11-01 09:49:16 +0100699 prompt "SMBIOS Product name" if !SMBIOS_PROVIDED_BY_MOBO
700 string
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200701 depends on GENERATE_SMBIOS_TABLES
702 default MAINBOARD_PART_NUMBER
703 help
704 Override the default Product name stored in SMBIOS structures.
705
Julien Viard de Galbert9d231a92018-02-28 13:39:55 +0100706config SMBIOS_ENCLOSURE_TYPE
707 hex
708 depends on GENERATE_SMBIOS_TABLES
709 default 0x09 if SYSTEM_TYPE_LAPTOP
Duncan Laurie8312df42019-02-01 11:33:57 -0800710 default 0x1e if SYSTEM_TYPE_TABLET
711 default 0x1f if SYSTEM_TYPE_CONVERTIBLE
712 default 0x20 if SYSTEM_TYPE_DETACHABLE
Julien Viard de Galbert9d231a92018-02-28 13:39:55 +0100713 default 0x03
714 help
715 System Enclosure or Chassis Types as defined in SMBIOS specification.
Duncan Laurie8312df42019-02-01 11:33:57 -0800716 The default value is SMBIOS_ENCLOSURE_DESKTOP (0x03) but laptop,
717 convertible, or tablet enclosure will be used if the appropriate
718 system type is selected.
Julien Viard de Galbert9d231a92018-02-28 13:39:55 +0100719
Myles Watson45bb25f2009-09-22 18:49:08 +0000720endmenu
721
Martin Roth21c06502016-02-04 19:52:27 -0700722source "payloads/Kconfig"
Peter Stugea758ca22009-09-17 16:21:31 +0000723
Uwe Hermann168b11b2009-10-07 16:15:40 +0000724menu "Debugging"
725
Nico Huberd67edca2018-11-13 19:28:07 +0100726comment "CPU Debug Settings"
727source "src/cpu/*/Kconfig.debug"
728
729comment "General Debug Settings"
730
Uwe Hermann168b11b2009-10-07 16:15:40 +0000731# TODO: Better help text and detailed instructions.
Patrick Georgi0588d192009-08-12 15:00:51 +0000732config GDB_STUB
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000733 bool "GDB debugging support"
Rudolf Marek65888022012-03-25 20:51:16 +0200734 default n
Denis 'GNUtoo' Carikli3747ba12015-12-10 22:04:56 +0100735 depends on CONSOLE_SERIAL
Patrick Georgi0588d192009-08-12 15:00:51 +0000736 help
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000737 If enabled, you will be able to set breakpoints for gdb debugging.
Stefan Reinauer8677a232010-12-11 20:33:41 +0000738 See src/arch/x86/lib/c_start.S for details.
Patrick Georgi0588d192009-08-12 15:00:51 +0000739
Denis 'GNUtoo' Cariklie4cece02012-06-22 15:56:37 +0200740config GDB_WAIT
Denis 'GNUtoo' Carikli7d234f22015-12-10 21:58:52 +0100741 bool "Wait for a GDB connection in the ramstage"
Denis 'GNUtoo' Cariklie4cece02012-06-22 15:56:37 +0200742 default n
743 depends on GDB_STUB
744 help
Denis 'GNUtoo' Carikli7d234f22015-12-10 21:58:52 +0100745 If enabled, coreboot will wait for a GDB connection in the ramstage.
746
Denis 'GNUtoo' Cariklie4cece02012-06-22 15:56:37 +0200747
Julius Wernerd82e0cf2015-02-17 17:27:23 -0800748config FATAL_ASSERTS
749 bool "Halt when hitting a BUG() or assertion error"
750 default n
751 help
752 If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
753
Nico Huber371a6672018-11-13 22:06:40 +0100754config HAVE_DEBUG_GPIO
755 bool
756
757config DEBUG_GPIO
758 bool "Output verbose GPIO debug messages"
759 depends on HAVE_DEBUG_GPIO
760
Stefan Reinauerfe422182012-05-02 16:33:18 -0700761config DEBUG_CBFS
762 bool "Output verbose CBFS debug messages"
763 default n
Stefan Reinauerfe422182012-05-02 16:33:18 -0700764 help
765 This option enables additional CBFS related debug messages.
766
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000767config HAVE_DEBUG_RAM_SETUP
768 def_bool n
769
Uwe Hermann01ce6012010-03-05 10:03:50 +0000770config DEBUG_RAM_SETUP
771 bool "Output verbose RAM init debug messages"
772 default n
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000773 depends on HAVE_DEBUG_RAM_SETUP
Uwe Hermann01ce6012010-03-05 10:03:50 +0000774 help
775 This option enables additional RAM init related debug messages.
776 It is recommended to enable this when debugging issues on your
777 board which might be RAM init related.
778
779 Note: This option will increase the size of the coreboot image.
780
781 If unsure, say N.
782
Myles Watson80e914f2010-06-01 19:25:31 +0000783config DEBUG_PIRQ
784 bool "Check PIRQ table consistency"
785 default n
786 depends on GENERATE_PIRQ_TABLE
787 help
788 If unsure, say N.
789
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000790config HAVE_DEBUG_SMBUS
791 def_bool n
792
Uwe Hermann01ce6012010-03-05 10:03:50 +0000793config DEBUG_SMBUS
794 bool "Output verbose SMBus debug messages"
795 default n
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000796 depends on HAVE_DEBUG_SMBUS
Uwe Hermann01ce6012010-03-05 10:03:50 +0000797 help
798 This option enables additional SMBus (and SPD) debug messages.
799
800 Note: This option will increase the size of the coreboot image.
801
802 If unsure, say N.
803
804config DEBUG_SMI
805 bool "Output verbose SMI debug messages"
806 default n
807 depends on HAVE_SMI_HANDLER
Nico Huber9e53db42018-06-05 22:34:08 +0200808 select SPI_FLASH_SMM if SPI_CONSOLE || CONSOLE_SPI_FLASH
Uwe Hermann01ce6012010-03-05 10:03:50 +0000809 help
810 This option enables additional SMI related debug messages.
811
812 Note: This option will increase the size of the coreboot image.
813
814 If unsure, say N.
815
Uwe Hermanna953f372010-11-10 00:14:32 +0000816# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
817# printk(BIOS_DEBUG, ...) calls.
818config DEBUG_MALLOC
Stefan Reinauer95a63962012-11-13 17:00:01 -0800819 prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
820 bool
Uwe Hermanna953f372010-11-10 00:14:32 +0000821 default n
Uwe Hermanna953f372010-11-10 00:14:32 +0000822 help
823 This option enables additional malloc related debug messages.
824
825 Note: This option will increase the size of the coreboot image.
826
827 If unsure, say N.
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300828
829# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
830# printk(BIOS_DEBUG, ...) calls.
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300831config DEBUG_ACPI
Stefan Reinauer95a63962012-11-13 17:00:01 -0800832 prompt "Output verbose ACPI debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
833 bool
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300834 default n
835 help
836 This option enables additional ACPI related debug messages.
837
838 Note: This option will slightly increase the size of the coreboot image.
839
840 If unsure, say N.
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300841
Kyösti Mälkki66277952018-12-31 15:22:34 +0200842config DEBUG_CONSOLE_INIT
843 bool "Debug console initialisation code"
844 default n
845 help
846 With this option printk()'s are attempted before console hardware
847 initialisation has been completed. Your mileage may vary.
848
849 Typically you will need to modify source in console_hw_init() such
850 that a working console appears before the one you want to debug.
851
852 If unsure, say N.
853
Uwe Hermanna953f372010-11-10 00:14:32 +0000854# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
855# printk(BIOS_DEBUG, ...) calls.
Myles Watson6c9bc012010-09-07 22:30:15 +0000856config REALMODE_DEBUG
Stefan Reinauer95a63962012-11-13 17:00:01 -0800857 prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
858 bool
Myles Watson6c9bc012010-09-07 22:30:15 +0000859 default n
Peter Stuge5015f792010-11-10 02:00:32 +0000860 depends on PCI_OPTION_ROM_RUN_REALMODE
Myles Watson6c9bc012010-09-07 22:30:15 +0000861 help
862 This option enables additional x86emu related debug messages.
863
864 Note: This option will increase the time to emulate a ROM.
865
866 If unsure, say N.
867
Uwe Hermann01ce6012010-03-05 10:03:50 +0000868config X86EMU_DEBUG
869 bool "Output verbose x86emu debug messages"
870 default n
871 depends on PCI_OPTION_ROM_RUN_YABEL
872 help
873 This option enables additional x86emu related debug messages.
874
875 Note: This option will increase the size of the coreboot image.
876
877 If unsure, say N.
878
879config X86EMU_DEBUG_JMP
880 bool "Trace JMP/RETF"
881 default n
882 depends on X86EMU_DEBUG
883 help
884 Print information about JMP and RETF opcodes from x86emu.
885
886 Note: This option will increase the size of the coreboot image.
887
888 If unsure, say N.
889
890config X86EMU_DEBUG_TRACE
891 bool "Trace all opcodes"
892 default n
893 depends on X86EMU_DEBUG
894 help
895 Print _all_ opcodes that are executed by x86emu.
Stefan Reinauer14e22772010-04-27 06:56:47 +0000896
Uwe Hermann01ce6012010-03-05 10:03:50 +0000897 WARNING: This will produce a LOT of output and take a long time.
898
899 Note: This option will increase the size of the coreboot image.
900
901 If unsure, say N.
902
903config X86EMU_DEBUG_PNP
904 bool "Log Plug&Play accesses"
905 default n
906 depends on X86EMU_DEBUG
907 help
908 Print Plug And Play accesses made by option ROMs.
909
910 Note: This option will increase the size of the coreboot image.
911
912 If unsure, say N.
913
914config X86EMU_DEBUG_DISK
915 bool "Log Disk I/O"
916 default n
917 depends on X86EMU_DEBUG
918 help
919 Print Disk I/O related messages.
920
921 Note: This option will increase the size of the coreboot image.
922
923 If unsure, say N.
924
925config X86EMU_DEBUG_PMM
926 bool "Log PMM"
927 default n
928 depends on X86EMU_DEBUG
929 help
930 Print messages related to POST Memory Manager (PMM).
931
932 Note: This option will increase the size of the coreboot image.
933
934 If unsure, say N.
935
936
937config X86EMU_DEBUG_VBE
938 bool "Debug VESA BIOS Extensions"
939 default n
940 depends on X86EMU_DEBUG
941 help
942 Print messages related to VESA BIOS Extension (VBE) functions.
943
944 Note: This option will increase the size of the coreboot image.
945
946 If unsure, say N.
947
948config X86EMU_DEBUG_INT10
949 bool "Redirect INT10 output to console"
950 default n
951 depends on X86EMU_DEBUG
952 help
953 Let INT10 (i.e. character output) calls print messages to debug output.
954
955 Note: This option will increase the size of the coreboot image.
956
957 If unsure, say N.
958
959config X86EMU_DEBUG_INTERRUPTS
960 bool "Log intXX calls"
961 default n
962 depends on X86EMU_DEBUG
963 help
964 Print messages related to interrupt handling.
965
966 Note: This option will increase the size of the coreboot image.
967
968 If unsure, say N.
969
970config X86EMU_DEBUG_CHECK_VMEM_ACCESS
971 bool "Log special memory accesses"
972 default n
973 depends on X86EMU_DEBUG
974 help
975 Print messages related to accesses to certain areas of the virtual
976 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
977
978 Note: This option will increase the size of the coreboot image.
979
980 If unsure, say N.
981
982config X86EMU_DEBUG_MEM
983 bool "Log all memory accesses"
984 default n
985 depends on X86EMU_DEBUG
986 help
987 Print memory accesses made by option ROM.
988 Note: This also includes accesses to fetch instructions.
989
990 Note: This option will increase the size of the coreboot image.
991
992 If unsure, say N.
993
994config X86EMU_DEBUG_IO
995 bool "Log IO accesses"
996 default n
997 depends on X86EMU_DEBUG
998 help
999 Print I/O accesses made by option ROM.
1000
1001 Note: This option will increase the size of the coreboot image.
1002
1003 If unsure, say N.
1004
Denis 'GNUtoo' Carikli4cdc5d62013-05-15 00:19:49 +02001005config X86EMU_DEBUG_TIMINGS
1006 bool "Output timing information"
1007 default n
Kyösti Mälkki91945fb2019-07-10 15:10:22 +03001008 depends on X86EMU_DEBUG && HAVE_MONOTONIC_TIMER
Denis 'GNUtoo' Carikli4cdc5d62013-05-15 00:19:49 +02001009 help
1010 Print timing information needed by i915tool.
1011
1012 If unsure, say N.
1013
Stefan Reinauer1c56d9b2012-05-10 11:27:32 -07001014config DEBUG_SPI_FLASH
1015 bool "Output verbose SPI flash debug messages"
1016 default n
1017 depends on SPI_FLASH
1018 help
1019 This option enables additional SPI flash related debug messages.
1020
Stefan Reinauer8e073822012-04-04 00:07:22 +02001021if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
1022# Only visible with the right southbridge and loglevel.
1023config DEBUG_INTEL_ME
1024 bool "Verbose logging for Intel Management Engine"
1025 default n
1026 help
1027 Enable verbose logging for Intel Management Engine driver that
1028 is present on Intel 6-series chipsets.
1029endif
1030
Rudolf Marek7f0e9302011-09-02 23:23:41 +02001031config TRACE
1032 bool "Trace function calls"
1033 default n
1034 help
1035 If enabled, every function will print information to console once
1036 the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
1037 the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
Ben Gardner8420ad42015-11-18 10:46:53 -06001038 of calling function. Please note some printk related functions
Rudolf Marek7f0e9302011-09-02 23:23:41 +02001039 are omitted from trace to have good looking console dumps.
Stefan Reinauerd37ab452012-12-18 16:23:28 -08001040
1041config DEBUG_COVERAGE
1042 bool "Debug code coverage"
1043 default n
1044 depends on COVERAGE
1045 help
1046 If enabled, the code coverage hooks in coreboot will output some
1047 information about the coverage data that is dumped.
1048
Jonathan Neuschäferfc04f9b2016-06-29 21:59:32 +02001049config DEBUG_BOOT_STATE
1050 bool "Debug boot state machine"
1051 default n
1052 help
1053 Control debugging of the boot state machine. When selected displays
1054 the state boundaries in ramstage.
1055
Nico Hubere84e62542016-10-05 17:43:56 +02001056config DEBUG_ADA_CODE
1057 bool "Compile debug code in Ada sources"
1058 default n
1059 help
1060 Add the compiler switch `-gnata` to compile code guarded by
1061 `pragma Debug`.
1062
Simon Glass46255f72018-07-12 15:26:07 -06001063config HAVE_EM100_SUPPORT
1064 bool "Platform can support the Dediprog EM100 SPI emulator"
1065 help
1066 This is enabled by platforms which can support using the EM100.
1067
1068config EM100
1069 bool "Configure image for EM100 usage"
1070 depends on HAVE_EM100_SUPPORT
1071 help
1072 The Dediprog EM100 SPI emulator allows fast loading of new SPI images
1073 over USB. However it only supports a maximum SPI clock of 20MHz and
1074 single data output. Enable this option to use a 20MHz SPI clock and
1075 disable "Dual Output Fast Read" Support.
1076
1077 On AMD platforms this changes the SPI speed at run-time if the
1078 mainboard code supports this. On supported Intel platforms this works
1079 by changing the settings in the descriptor.bin file.
1080
Uwe Hermann168b11b2009-10-07 16:15:40 +00001081endmenu
1082
Martin Roth8e4aafb2016-12-15 15:25:15 -07001083
1084###############################################################################
1085# Set variables with no prompt - these can be set anywhere, and putting at
1086# the end of this file gives the most flexibility.
Nico Huber3db76532017-05-18 18:07:34 +02001087
1088source "src/lib/Kconfig"
1089
Myles Watsond73c1b52009-10-26 15:14:07 +00001090config ENABLE_APIC_EXT_ID
1091 bool
1092 default n
Myles Watson2e672732009-11-12 16:38:03 +00001093
1094config WARNINGS_ARE_ERRORS
1095 bool
Edward O'Callaghan63f6dc72014-11-18 03:17:54 +11001096 default y
Patrick Georgi436f99b2009-11-27 16:55:13 +00001097
Peter Stuge51eafde2010-10-13 06:23:02 +00001098# The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
1099# POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
1100# mutually exclusive. One of these options must be selected in the
1101# mainboard Kconfig if the chipset supports enabling and disabling of
1102# the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
1103# in mainboard/Kconfig to know if the button should be enabled or not.
1104
1105config POWER_BUTTON_DEFAULT_ENABLE
1106 def_bool n
1107 help
1108 Select when the board has a power button which can optionally be
1109 disabled by the user.
1110
1111config POWER_BUTTON_DEFAULT_DISABLE
1112 def_bool n
1113 help
1114 Select when the board has a power button which can optionally be
1115 enabled by the user, e.g. when the board ships with a jumper over
1116 the power switch contacts.
1117
1118config POWER_BUTTON_FORCE_ENABLE
1119 def_bool n
1120 help
1121 Select when the board requires that the power button is always
1122 enabled.
1123
1124config POWER_BUTTON_FORCE_DISABLE
1125 def_bool n
1126 help
1127 Select when the board requires that the power button is always
1128 disabled, e.g. when it has been hardwired to ground.
1129
1130config POWER_BUTTON_IS_OPTIONAL
1131 bool
1132 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
1133 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
1134 help
1135 Internal option that controls ENABLE_POWER_BUTTON visibility.
Duncan Laurie72748002013-10-31 08:26:23 -07001136
1137config REG_SCRIPT
1138 bool
Duncan Laurie72748002013-10-31 08:26:23 -07001139 default n
1140 help
1141 Internal option that controls whether we compile in register scripts.
Furquan Shaikh99ac98f2014-04-23 10:18:48 -07001142
Furquan Shaikh99ac98f2014-04-23 10:18:48 -07001143config MAX_REBOOT_CNT
1144 int
1145 default 3
Timothy Pearson17ada2e2015-03-18 01:31:34 -05001146 help
1147 Internal option that sets the maximum number of bootblock executions allowed
1148 with the normal image enabled before assuming the normal image is defective
Vadim Bendebury9c9c3362014-07-23 09:40:02 -07001149 and switching to the fallback image.
Martin Roth59ff3402016-02-09 09:06:46 -07001150
Martin Roth8e4aafb2016-12-15 15:25:15 -07001151config UNCOMPRESSED_RAMSTAGE
1152 bool
1153
1154config NO_XIP_EARLY_STAGES
1155 bool
1156 default n if ARCH_X86
1157 default y
1158 help
1159 Identify if early stages are eXecute-In-Place(XIP).
1160
Martin Roth8e4aafb2016-12-15 15:25:15 -07001161config EARLY_CBMEM_LIST
1162 bool
1163 default n
1164 help
1165 Enable display of CBMEM during romstage and postcar.
1166
1167config RELOCATABLE_MODULES
1168 bool
1169 help
1170 If RELOCATABLE_MODULES is selected then support is enabled for
1171 building relocatable modules in the RAM stage. Those modules can be
1172 loaded anywhere and all the relocations are handled automatically.
1173
1174config NO_STAGE_CACHE
1175 bool
Kyösti Mälkki0a4457f2019-08-01 20:29:14 +03001176 default y if !HAVE_ACPI_RESUME || !RELOCATABLE_RAMSTAGE
Martin Roth8e4aafb2016-12-15 15:25:15 -07001177 help
1178 Do not save any component in stage cache for resume path. On resume,
1179 all components would be read back from CBFS again.
1180
1181config GENERIC_GPIO_LIB
1182 bool
1183 help
1184 If enabled, compile the generic GPIO library. A "generic" GPIO
1185 implies configurability usually found on SoCs, particularly the
1186 ability to control internal pull resistors.
1187
Martin Roth8e4aafb2016-12-15 15:25:15 -07001188config BOOTBLOCK_CUSTOM
1189 # To be selected by arch, SoC or mainboard if it does not want use the normal
1190 # src/lib/bootblock.c#main() C entry point.
1191 bool
1192
1193config C_ENVIRONMENT_BOOTBLOCK
1194 # To be selected by arch or platform if a C environment is available during the
1195 # bootblock. Normally this signifies availability of RW memory (e.g. SRAM).
1196 bool
1197
Martin Roth75e5cb72016-12-15 15:05:37 -07001198###############################################################################
1199# Set default values for symbols created before mainboards. This allows the
1200# option to be displayed in the general menu, but the default to be loaded in
1201# the mainboard if desired.
1202config COMPRESS_RAMSTAGE
1203 default y if !UNCOMPRESSED_RAMSTAGE
1204
1205config COMPRESS_PRERAM_STAGES
1206 depends on !ARCH_X86
1207 default y
1208
1209config INCLUDE_CONFIG_FILE
1210 default y
1211
Martin Roth75e5cb72016-12-15 15:05:37 -07001212config BOOTSPLASH_FILE
1213 depends on BOOTSPLASH_IMAGE
1214 default "bootsplash.jpg"
1215
1216config CBFS_SIZE
1217 default ROM_SIZE
Subrata Banikb5962a92019-06-08 12:29:02 +05301218
1219config HAVE_BOOTBLOCK
1220 bool
1221 default y
1222
1223config HAVE_VERSTAGE
1224 bool
1225 depends on VBOOT_SEPARATE_VERSTAGE
1226 default y
1227
1228config HAVE_ROMSTAGE
1229 bool
1230 default y
1231
1232config HAVE_POSTCAR
1233 bool
1234 depends on POSTCAR_STAGE
1235 default y
1236
1237config HAVE_RAMSTAGE
1238 bool
1239 default n if RAMPAYLOAD
1240 default y